Actel Announces the Industry's First Family of System Programmable Gate Arrays; ES "System-on-a-Chip" Family Offers up to 400,000 Programmable Gates; includes Embedded ASIC Cores.

SUNNYVALE, Calif--(BUSINESS WIRE)--Oct. 21, 1996--Actel Corporation (NASDAQ:ACTL) today announced the industry's first system programmable gate array (SPGA), the ES (embedded SPGA) family, and its first member -- the A65ES100 -- a 100,000-gate device based on the company's new reprogrammable ES architecture.

SPGAs are programmable systems-on-a-chip that offer industry-leading logic integration, predicable targeting of re-useable soft blocks or application-specific cores, and cost efficiency approaching traditional masked programmed gate arrays.

FPGA and ASIC designers transitioning to SPGAs will benefit from significantly faster time-to-market, increased cost effectiveness, and greater flexibility when designing next generation communications, digital signal processing, multimedia, embedded systems, and computer applications.

"For designers to achieve dramatic improvements in productivity, they need programmable architectures that enable design re-use for both soft intellectual property (IP) blocks and embedded cores," said Robert Nalesnik, director of product marketing for Actel. "Our new ES family provides the capacity, cost-effectiveness, predictability, and system features to implement true programmable systems-on-silicon."

The ES product family will consist of eight devices: six reprogrammable SPGAs ranging from 50,000 to 400,000 gates, and two devices that include embedded cores. The embedded SPGA devices integrate mask-programmable ASIC blocks into the programmable ES architecture, allowing designers to target system functional blocks into programmable logic for maximum flexibility, or into the ASIC area for improved performance cost efficiency.

ES Architecture

Actel developed its new ES architecture to enable programmable systems-on-silicon. "Current FPGA architectures are not sufficient to achieve high-capacity in a cost-effective manner," said Nalesnik. "With ES, we rethought the fundamental issues of predictability and routability to develop an architecture that is more predictable and twice as efficient as current SRAM-based FPGAs."

The ES architecture is switch technology-independent, so products can utilize SRAM, antifuse, or flash as the basic programming element. Actel is introducing the initial ES family based on reprogrammable, three-layer metal CMOS SRAM technology. The architecture, coupled with a 0.35 micron process, achieves an incredible 160kmil(squared) die size for 100,000 gates, which is significantly smaller than any similar part currently available. With 0.25-micron process geometry, capacities in excess of 1 million gates are achievable. Actel envisions further performance and density improvements with antifuse or flash in the future.

The key to the architectural efficiencies is a technology Actel calls MultiDrive active routing. Separate transistors are used to implement logic and to drive the interconnects. By separating these functions, more transistors can be included per chip, which translates to smaller die size and more efficient and lower cost designs. Additionally, interconnect drivers are tailored to routing length, which provides high-performance even for cross-chip routing.

The ES architecture also makes greater use of hierarchy than current programmable architectures. For example, Actel's 100,000-gate device has seven levels of routing hierarchy. Unique to this feature is a constant, maximum routing delay associated with each level, providing the device with fanout independent delays. Regardless of the number of logic elements being driven, the delay will always be constant, making the chip's performance fully predictable. As designs increase above 50,000 gates, predictable timing is critical to on-time completion.

The Actel ES Family

Devices in Actel's ES family are targeted for high-performance systems. Programmable functions should boast 75 Megahertz (MHz) system performance and 200MHz datapath throughput. Embedded functions operate at approximately twice that speed and require one-fifth the area; however, those sections implemented in ASIC technology are not programmable.

ES devices will include embedded dual-port RAM blocks for high-speed data acquisition. The A65ES100 includes 16KB of RAM, organized as eight 2KB blocks, with 7ns access times.

Other ES features that support single chip system design include:

-- In-System Programming -- devices can be reconfigured on the board and in the field.

-- ClockSync -- Multiple Digital Phase Locked Loops (DPLL) -- provides balancing of multiple system clocks. Also enables effective clock-to-output delays to be reduced from 7ns to 0ns.

-- Flexible I/Os -- includes PCI compliance, dual-voltage interface, and four programmable slew rates per I/O.

-- High Pin Count Package Options -- the initial A65ES100 device will be supported in 208- and 240-pm PQFP, 240- and 432-pin SBGA, and 391-pin PPGA packages.

-- Powerful test and debug features:

-- DesignSafe -- provides the capability to secure the

contents of the device by data encryption, which allows

users to protect their proprietary data.

-- ActionProbe -- provides dynamic probing of internal nodes

for on-chip debugging.

Both DesignSafe and ActionProbe capabilities have been available in Actel's antifuse parts, but are offered for the first time in an SRAM device as part of the ES family.

ES Software Support

Actel offers all of the components for designers to move to SPGA designs quickly and efficiently. A new version of Actel's Designer Series software will support Actel SPGAs.

Designer Series is a comprehensive set of high performance, automated design tools: its sophisticated graphical design flow manager and object-oriented database virtually eliminate the learning curve for complex designs. Front-end design will be supported on major EDA platforms, including Antares, Cadence, Mentor, Mine/IST, Synopsys, Synplicity, and Viewlogic.

Actel has access to a large portfolio of intellectual property (IP) functions through the CoreHDI. Alliance. Over 100 system function blocks are available in the areas of communications, digital signal processing, bus interface, and microprocessors. These functions are available in VHDL, or Verilog HDL, and are currently being ported to the ES family.

Pricing and Availability

Samples of the A65ES100 will be available in November, with production units available in the first half of 1997. The A65ES100 will be priced at $469 in sample quantities, and at $348 in production in a 240-PQFP (plastic quad flat pack) package. In a 432-SBGA (super ball grid array) package, samples are priced at $495 and production pricing is $374. Volume pricing on maturity is expected to be less than $100. Designer Series software to support the A65ES100 will also be available in November.

The first embedded SPGA device, the A65ES25/25, will contain 25,000 programmable logic gates and 25,000 mask programmable gates. Availability is expected in the summer of 1997.

About Actel

Actel is dedicated to providing the best programmable logic solutions, giving logic designers the capability and confidence to move to high complexity designs with success. The Company is the world's leading supplier of antifuse-based field programmable gate arrays (FPGAs) and associated software development tools. FPGAs are used by designers of communications, computer, medical, military/aerospace, industrial control, and other electronic systems to differentiate their products and get them to market faster.

Actel introduced the first programmable systems-on-silicon, based on SRAM technology, which inaugurated a new class of PLDs: SPGAs or system programmable gate arrays. Actel is traded on NASDAQ National Market under the symbol ACTL, and is located at 955 East Arques Avenue, Sunnyvale, Calif. 94086-4533. Telephone: [phone]. Internet: http://www.actel.com. -0-

Note to Editors: Actel is a registered trademark of Actel Corporation. All other trademarks are property of their respective owners.

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