Accellera Hosts Free Luncheon Workshops & Open Member Meeting at DATE; March 8th & 10th, Munich, Germany.MUNICH, Germany -- Accellera, the electronics industry organization focused on electronic design automation (EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. ) standards (based in Napa, CA, USA), announced today that Accellera will host 2 Solutions Workshops and an open Member Meeting at the Design Automation & Test in Europe (DATE) conference in Munich, Germany on March 8th and March 10th. Solutions Workshop 1 will cover Applying a SystemVerilog Testbench to a VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. or Verilog Design and will be presented by Doulos and Mentor Graphics Mentor Graphics, Inc (NASDAQ: MENT) is a US-based multinational corporation dealing in electronic design automation (EDA) for electrical engineering and electronics, as of 2004, ranked third in the EDA industry it helped create. . Solutions Workshop 2 will address Assertion-based Verification with SystemVerilog and will be presented by Doulos and Synopsys. Accellera's Open Member Meeting will offer an update of IEEE (Institute of Electrical and Electronics Engineers, New York, www.ieee.org) A membership organization that includes engineers, scientists and students in electronics and allied fields. and Accellera technical efforts and a panel discussion focused on the topic of EDA standards in Europe.
Dates, Times, Locations, Presentations, Registration Information
Tuesday, 8th March, Room 21
-- 13:00 - 14:30, Buffet lunch from 12:00, Solutions Workshop 1
Applying a SystemVerilog Testbench to a VHDL or Verilog Design
To register, please visit
http://www.doulos.com/content/events/date/workshop1.php.
-- 18:00-20:00, Accellera Open Member Meeting
IEEE & Accellera Technical Committee reports followed by a
panel discussing the European View of Standards
To register, please visit www.accellera.org.
Thursday, 10th March, Room C12
-- 13:00 - 14:30, Buffet lunch from 12:00, Solutions Workshop 2
Assertion-based Verification with SystemVerilog
To register, please visit
http://www.doulos.com/content/events/date/workshop2.php.
The Accellera events will take place during DATE 2005 (www.date-conference.com) at the ICM ICM Intercom ICM Integrated Crop Management ICM International Congress of Mathematicians ICM Information Classification and Management ICM Intelligent Contact Management (Cisco) ICM International Creative Management , MESSE, Munich, Germany. About Accellera Accellera provides design standards Design standards Specifications of materials, physical measurements, processes, performance of products, and characteristics of services rendered. Design standards may be established by individual manufacturers, trade associations, and national or for quick availability and use in the electronics industry. The organization and its members cooperatively deliver much-needed EDA standards that lower the cost of designing commercial IC and EDA products. As a result of Accellera's partnership with the IEEE, Accellera standards are provided to the IEEE standards body for formalization for·mal·ize tr.v. for·mal·ized, for·mal·iz·ing, for·mal·iz·es 1. To give a definite form or shape to. 2. a. To make formal. b. and ongoing change control. For more information about Accellera, please visit www.accellera.org. Accellera acknowledges trademarks or registered trademarks of other organizations for their respective products and services. |
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