Accellera Announces Transistor-Level Behavioral Modeling Capability, Approves Verilog-AMS 2.2 Standard.

SAN JOSE, Calif. -- Accellera, the electronics industry organization focused on electronic design automation (EDA) standards, today announced that its Board and Technical Committee members -- systems, semiconductor and design tool companies -- have approved Verilog-AMS 2.2 as an Accellera standard for analog and mixed-signal design and simulation.

Verilog-AMS encompasses analog and mixed-signal extensions to IEEE Std. 1364(TM) Verilog Hardware Description Language, which is widely used in digital circuit design and verification.

Now available as an Accellera standard, the Verilog-AMS 2.2 Language Reference Manual (LRM) includes new features to aid the description of semiconductor devices, such as transistors and diodes, in a standard language. Verilog-AMS benefits users by allowing them to describe and simulate the analog portions of complicated system-on-a-chip (SoC) designs in the same language as the digital portions. Several EDA vendors offer products that accept Verilog-AMS descriptions and perform mixed-signal simulations.

"Accellera is pleased to introduce Verilog-AMS 2.2 to the electronics community as an industry language standard," said Dennis Brophy, Accellera Chairman. "This is an enabling technology to help develop new generation of device models to address nanotechnology and allow designers to verify innovative circuits with tools that support this new version of Verilog-AMS."

"With the release of LRM 2.2, Verilog-AMS is poised to become the standard language of compact modeling, with support for a range of EDA tools -- from semiconductor characterization and parameter extraction tools through traditional analog circuit simulators to radio-frequency (RF) simulators and 'fast-Spice' simulators," said Geoffrey Coram, chairman of the Accellera subcommittee that developed the new Language Reference Manual (LRM). "Compact model developers are already switching to Verilog-AMS for the development of the next-generation MOSFET model."

"LRM2.2 is an extremely important milestone in the standardization efforts of the Verilog-AMS language, by providing analog designers the ability to write behavioral compact models using Verilog-AMS. The language provides an ability to simulate transistor models very efficiently without any loss in accuracy," noted Srikanth Chandrasekaran, chairman of the Verilog-AMS committee. He added, "Looking ahead at 2005 and beyond, the Verilog-AMS committee will focus on a closer integration with the IEEE 1364 (Verilog) and P1800 (SystemVerilog) standards, and extend the scope of Verilog-AMS language to address the needs of RF designers. The latest version of Verilog-AMS provides an excellent platform to accomplish the task at hand for the technical committee."

What's New

The primary goal in the development of Verilog-AMS 2.2 was addition of language constructs to support compact models, that is, behavioral descriptions of semiconductor devices. As semiconductor manufacturing processes move to smaller geometries, new physical effects become important in relating the voltages and currents of transistors, resistors, diodes, and other devices. These effects are modeled by new equations in compact models, which must then be installed into analog simulators such as Spice. At present, each such installation must be performed directly in the simulator source code by each EDA company or through a proprietary modeling interface (usually based on the C programming language) by the semiconductor company for each simulator in use at that company. This cumbersome process is a barrier to the adoption of new compact models and thus impedes the migration of electronic design to the most advanced semiconductor processes.

Verilog-AMS is a simulator-independent standard language, and for that reason alone, it is a worthy replacement for the proprietary modeling interfaces. In addition, Verilog-AMS is a higher-level language than the C programming language in which compact models traditionally have been developed. It removes many tedious aspects of model development. For example, analog (Spice-like) circuit simulators require partial derivatives of the equations in a compact model for the Newton-Raphson algorithm; these derivatives must be written by hand in C, but Verilog-AMS simulators automatically compute the partial derivatives that are needed.

The new language constructs necessary for compact modeling were developed by an Accellera technical subcommittee with input from EDA vendors, semiconductor companies, and university researchers. The subcommittee members examined current compact models -- some implemented in simulators and some under development -- and identified common features that were hard or impossible to implement in Verilog-AMS 2.1. With an eye to the future merging of the languages, syntax from SystemVerilog was used to add these features when possible, and in all cases, conflict with existing IEEE 1364 (Verilog) or P1800 (SystemVerilog) syntax was avoided. Verilog-AMS will serve the needs of analog designers for many years.

Verilog-AMS Information & Support

For more information about Verilog-AMS or to obtain a copy of the LRM, please visit www.accellera.org. Accellera technical committees for Verilog-AMS and compact models can be found on http://www.eda.org/verilog-ams/.

About Accellera

Accellera provides design standards for quick availability and use in the electronics industry. The organization and its members cooperatively deliver much-needed EDA standards that lower the cost of designing commercial IC and EDA products. As a result of Accellera's partnership with the IEEE, Accellera standards are provided to the IEEE standards body for formalization and ongoing change control. For more information about Accellera, please visit www.accellera.org.

Accellera is located at 1370 Trancas Street #163, Napa, CA 94558. Phone: [phone], Fax: [phone], [e-mail].

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