Printer Friendly
The Free Library
19,573,952 articles and books
Member login
User name  
Password 
 
Join us Forgot password?

Accellera Announces Formation of Library Characterization & Interoperability Committee, Invites Electronics Industry to Participate.


Business Editors/High-Tech Writers

NAPA, Calif.--(BUSINESS WIRE)--May 3, 2004

Accellera, the electronics industry organization focused on language-based electronic design standards Design standards

Specifications of materials, physical measurements, processes, performance of products, and characteristics of services rendered. Design standards may be established by individual manufacturers, trade associations, and national or
, today announced the formation of a technical subcommittee to improve electronic design library characterization and tool interoperability. Accellera's Harmony subcommittee will define the common library characterization dataset needed for IC implementation and equivalent representation of the same data in Synopsys' Liberty(TM) format and the IEEE (Institute of Electrical and Electronics Engineers, New York, www.ieee.org) A membership organization that includes engineers, scientists and students in electronics and allied fields.  Std 1603(TM)-2003 (Advanced Library Format (ALF ALF - Algebraic Logic Functional language )).

The Harmony standard will improve EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board.  tool interoperability and reduce the need for tool-specific library extensions. It will specify the semantics of the library contents as well as a cross-reference between Liberty and ALF.

"Accellera welcomes every opportunity to extend our efforts to improve electronic design automation efficiency," noted Dennis Brophy, Chairman of Accellera. "Our Harmony group will improve design tool interoperability via a standard library format and address the challenges of next-generation semiconductor process technology characterization."

"The benefit of this work can be measured in cost reduction and improvements in quality of design libraries," added the technical subcommittee chairman, Dr. Wolfgang Roethig, Senior Design Engineering Manager, Design Solutions Center, NEC (NEC Corporation, Tokyo, www.nec.com, www.necus.com) An electronics conglomerate known in the U.S. for its monitors. In Japan, it had the lion's share of the PC market until the late 1990s (see PC 98).

NEC was founded in Tokyo in 1899 as Nippon Electric Company, Ltd.
 Electronics America, Inc., who initiated and leads this project. "With Liberty being the most widely used and ALF being the most comprehensive library format available to the industry, the technical subcommittee selected the strongest possible foundation for this project."

Invitation to Participate and Industry Support

Accellera invites the electronics industry to participate and review this standard. For more information, please visit www.eda.org/alf or www.accellera.org.

Participation in Accellera's Harmony subcommittee is open to all interested companies and individuals. To date, more than 12 companies are represented. These include Accellera members such as Artisan Components, Inc., Cadence Design Systems (company) Cadence Design Systems - A company that sells electronic design automation software and services.

http://cadence.com/.

See also Verilog.
 Inc., Mentor Graphics Mentor Graphics, Inc (NASDAQ: MENT) is a US-based multinational corporation dealing in electronic design automation (EDA) for electrical engineering and electronics, as of 2004, ranked third in the EDA industry it helped create.  Corp., NEC Electronics America and Synopsys Inc., among others.

Neal Carney, vice president of marketing at Artisan, added, "As a semiconductor IP provider, we focus on broad EDA tool interoperability support and welcome this standard to help better serve our customers."

About IEEE Std 1603-2003 (ALF)

IEEE Std 1603 standardizes the language and semantic representation for design libraries. It supports RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences;  to GDSII GDSII Graphic Design System II  descriptions of functional, electrical performance and layout views for technology libraries, scalable from cells to complex hierarchical design blocks.

About Liberty

Synopsys' widely used open library format, Liberty, includes the .lib, .plib, and SPM SPM - Sequential Parlog Machine  formats. Liberty is supported by more than 100 semiconductor vendors with more than 750 submicron libraries, and by more than 30 EDA vendors that supply over 75 production tools. It has evolved over 15 years along with technology and modeling needs and is a proven format, which can easily be extended to meet the needs of designers. Recent enhancements to Liberty include the addition of noise modeling capabilities, which will allow library suppliers and developers using this format to make their cell libraries ready for a comprehensive signal integrity flow for 130 and 90 nanometer designs. For more information on Liberty visit: http://www.synopsys.com/partners/tapin/lib_info.html.

About Accellera

Accellera provides design standards for quick availability and use in the electronics industry. The organization and its members cooperatively deliver much-needed EDA standards that lower the cost of designing integrated circuits Integrated circuits

Miniature electronic circuits produced within and upon a single semiconductor crystal, usually silicon. Integrated circuits range in complexity from simple logic circuits and amplifiers, about 1/20 in. (1.
 and EDA products. As a result of Accellera's long-standing, successful partnership with the IEEE, Accellera standards are provided to the IEEE standards body for formalization for·mal·ize  
tr.v. for·mal·ized, for·mal·iz·ing, for·mal·iz·es
1. To give a definite form or shape to.

2.
a. To make formal.

b.
 and ongoing change control. For more information about joining Accellera, please visit www.accellera.org.

Accellera is located at 1370 Trancas Street #163, Napa, CA 94558. Phone: 707-251-9977, Fax: 707-251-9877, info@accellera.org.


Acronyms and definition
ALF           Advanced Library Format
EDA           Electronic Design Automation
GDSII         General Data System. This format is used to tapeout or
               produce silicon
HDL           Hardware Description Language
IEEE          Institute of Electrical and Electronic Engineers
IC            Integrated Circuit
IP            Intellectual Property
RTL           Register Transfer Level
SoC           System on Chip
SPM           Scalable Polynomial Model


Liberty is a trademark of Synopsys, Inc.

All other trademarks and tradenames are the property of their respective holders.
COPYRIGHT 2004 Business Wire
No portion of this article can be reproduced without the express written permission from the copyright holder.
Copyright 2004, Gale Group. All rights reserved. Gale Group is a Thomson Corporation Company.

 Reader Opinion

Title:

Comment:



 

Article Details
Printer friendly Cite/link Email Feedback
Publication:Business Wire
Geographic Code:1USA
Date:May 3, 2004
Words:663
Previous Article:Allison & Partners Launches Technology Practice with New Palo Alto Office.
Next Article:Accellera Announces Award for Technical Achievement & Contributions to Its Design Automation Standards; Nominations Are Due May 14, 2004.
Topics:



Related Articles
ASC Releases Free ALF Parser; New Tool Expected to Encourage Use of the Advanced Library Format Standard for Electronic Circuit Design and Production.
Cadence Supports Accellera Standard; Lauds Choice of Sugar 2.0 as Standard Property Specification Language.
IBM PROPERTY SPECIFICATION LANGUAGE SELECTED AS NEW EDA STANDARD.
Synopsys EDA Developers' Forums to Focus on Interoperability And Verification Solutions; Synopsys CEO and Chairman Aart de Geus to Deliver Keynote...
Cadence Enables Open Interoperability for Next-Generation IEEE Verilog.
Synopsys Launches SystemVerilog Catalyst Program; More than 30 Companies Announce Support of SystemVerilog Standard.
ASTM announces round robins, new standards activities.
Cadence Contribution to Accellera Boosts Efforts to Standardize IC Design Kits for Designers.
Mentor Graphics Donation of SystemVerilog Assertion Version of Open Verification Library Accepted by Accellera.
Accellera committee focuses on standard coverage metrics.

Terms of use | Copyright © 2012 Farlex, Inc. | Feedback | For webmasters | Submit articles