Accelerant Transceiver Validates Teradyne Backplane in Less Than Two Days Using Lab in a Chip.

Business Editors/High-Tech Writers

BEAVERTON, Ore.--(BUSINESS WIRE)--Sept. 22, 2003

Teradyne's VHDM(R), VHDM-HSD(TM) and GbX(TM) Connector Platforms

Tested Using On-Chip Scope, BERT and Network Analyzer 

Accelerant Networks and Teradyne Inc.'s (NYSE:TER) Connection Systems Division (TCS) today announced successful validation and characterization of Teradyne's backplane reference platform in less than two days. The companies demonstrated error-free performance over multiple FR4 backplane channels originally designed for 3.125 Gigabits per second (Gb/s) transmission. Using Accelerant's new AN6000 family of low-power, high-speed SERDES (serializer-deserializer) transceiver products, greater than 6.25 Gb/s was achieved over a range of backplane trace lengths from 12 to 36 inches. The backplane characterization process was condensed from the typical requirement of six to nine months, by using Accelerant's unique Lab in a Chip suite of integrated test and diagnostics capabilities.

Current market trends underscore the preference of network, storage, and server system designers to develop upgrade paths that extend the life of existing chassis. While such upgrades appear straight forward, they have presented significant challenges. For example, when backplanes that were designed for up to 622 Megabits per second (Mb/s) transmission are upgraded with SERDES devices running at 3.125Gb/s and above, the transmitted signals experience dramatic loss, which exponentially increases the potential for errors.

"As development of higher-speed backplane systems increases, the need for improved diagnostics increases hand-in-hand. System developers need to incorporate a finer granularity of testing as they increase bandwidth, either with upgrades to existing chassis systems or for new platform development," said Michael Howard, principal analyst at Infonetics Research. "It's great to see innovation such as Accelerant's Lab in a Chip, which supports development of faster systems products, cheaper development process, and quicker time-to-market. Accelerant raises the bar for visibility and confidence in the reliability of transceiver links, while at the same time offering higher data rate performance in established interconnect systems."

"Accelerant's Lab in a Chip integrates system interconnect diagnostics within the high-speed transceiver cores with little impact on area or power," said Bob Lefferts, director of engineering for Accelerant Networks.

"The diagnostic capabilities are based on the on-chip Bit Error Rate Tester (BERT), built-in voltage and phase margining techniques, and an on-chip digital sampling scope per pin. The extensive margining techniques allow accurate estimation of system Bit Error Rate (BER) in a fraction of the time required when using the conventional 'wait-for-an-error' method. The sampling scope provides received eyes at the receiver inputs for eye mask analysis. The scope can also be used to capture unequalized pulse responses of the channel for signal integrity analysis. Finally, S-Parameters for through-channel, near-end, and far-end crosstalk can be generated using additional test modes in the transmitter and post processing of the time domain data," said Lefferts.

Accelerant's Lab in a Chip provides on-chip BERT, scope, and Vector Network Analyzer (VNA) capabilities without external connections to the channel. The equivalent stand-alone, external test, and diagnostic test equipment alone would total more than $200,000.

The impact of Accelerant's on-chip diagnostics extends through the entire life of the system, giving engineers a window into the backplane to examine physical interconnect characteristics. Prior to system production, as shown in the Teradyne testing, backplane characterization can be accomplished in days rather than months. In manufacturing, the diagnostics facilitate identification of defects and process monitoring to help improve manufacturing yields and throughput by as much as 50 percent. For deployed systems, on-chip diagnostics provide network managers a high level of confidence in system reliability where it counts most -- in the field.

"Through Accelerant's Lab in a Chip, system troubleshooting and debug can now be performed from the backplane out, rather than from the line card in, without requiring external test and diagnostic equipment," said Bill Hoppin, vice president of marketing for Accelerant Networks. "Looking at diagnostics from the backplane perspective provides more in-depth information about individual link status, resulting in finer granularity of system troubleshooting."

About the Teradyne Reference Backplane Validation

The Teradyne FR4 reference platform is used for characterizing system backplanes using its standard VHDM, VHDM-HSD and GBX connectors, which are widely deployed in network, storage, and server systems installed today. Accelerant and Teradyne demonstrated a BER better than 10e-20 over multiple 12-, 24-, 30- and 36-inch channels representing a wide range of possible design scenarios. The primary data rate of interest for this backplane system validation was 6.25 Gb/s. The 10 Gb/s capability of the Accelerant transceivers in this system was demonstrated, as well.

"Teradyne's VHDM, VHDM-HSD and GbX connector families are the connectors of choice for multi-gigabit backplane designs," said Lou Zajac, marketing manager for Teradyne Connection Systems. "Reliable SERDES devices that can maximize the performance characteristics of connectors are increasingly important as OEMs look to upgrade legacy systems in excess of 3 Gb/s."

About Accelerant Technology

Accelerant's intelligent silicon technology uses adaptive equalization to unlock hidden bandwidth in existing backplane interconnects common to network, server, and storage equipment currently installed worldwide. AN6000 backplane SERDES transceiver devices consume less than 1.4 Watts of power per quad 2:1 mux, operating four backplane ports at 10Gb/s and eight system I/O ports at 5Gb/s -- typically more than 50 percent lower power consumption than its competitors.

At speeds of 6.25Gb/s and above, these technological breakthroughs from Accelerant enable designers to overcome the physical limitations of backplanes designed for lower-speed transmission, including loss characteristics such as dielectric loss, crosstalk, and reflections.

Pricing and Availability

AN6000 series evaluation systems are available today and priced at $8,000. The evaluation system includes a MatLab software suite that allows full control and access to a built-in BERT, vector network analyzer, and digital scope diagnostics integrated into the silicon.

About Accelerant

Accelerant Networks is a fabless semiconductor company delivering intelligent silicon transceivers that unlock new levels of bandwidth from low-cost interconnects such as backplanes and cables used commonly in the network, storage, and server markets. The company is headquartered in Beaverton, Ore., with sales and application offices in Silicon Valley, as well as a nationwide network of sales representatives. For more information visit Accelerant on the web at www.accelerant.net.

About Teradyne Connection Systems

Teradyne Connection Systems (TCS), a division of Boston-based Teradyne, Inc. (NYSE:TER), provides total system solutions, with high-performance circuits, high-speed, high-density connectors, multi-gigabit backplane assemblies and complete system integration and test services. TCS enables industry-leading equipment manufacturers to meet their demanding technology, reliability and time-to-market requirements. For more information visit http://www.teradyne.com/tcs.

This press release can be viewed online at: http://www.accelerant.net/news_events/releases/2003922.htm