Accelerant Combines World's First Binary DFE Transceiver with Industry's Lowest Power PAM4 10Gb/S Backplane Core at 0.22 Watts Per Link.
Business Editors/High-Tech Writers
BEAVERTON, Ore.--(BUSINESS WIRE)--Oct. 27, 2003
-- 0% overhead mode enables line rate OC-192 or 10GE per
backplane differential pair Differential pair is a pair of conductors with special characteristics, used for differential signaling.
Examples of the differential pair include:
-- Binary Decision Feedback Equalization In communications, techniques used to reduce distortion and compensate for signal loss (attenuation) over long distances. (DFE DFE Design For the Environment
DFE Digital Front End
DFE Decision Feedback Equalization
DFE Decision Feedback Equalizer
DFE Department For Education (UK)
DFE Dietary Folate Equivalent ) interoperates with
legacy 1-5Gb/s SERDES See serializer/deserializer.
Accelerant Networks today announced availability of the highest performance, lowest power SERDES device available today for backplane applications. The AN6420 is the newest member of its AN6000 family of high-speed SERDES transceivers that offers breakthrough 0 percent overhead technology for the highest performance, lowest power SERDES device available, demonstrating line rates of 10 Gigabit payloads (Ethernet or OC-192) across existing backplane differential pairs, without increasing the existing power budget.
The device's four backplane interface cores require less than 870mW per 40 Gb/s total payload, operating across FR4 material and two backplane connectors. This makes the AN6420 the highest performance, lowest power SERDES device available today for backplane applications.
The AN6420 operates at 6.25 Gigabits per second (Gb/s) with a demonstrated rate up to 10 Gb/s user payload in PAM4 multilevel mul·ti·lev·el
Having several levels: a multilevel parking garage.
Adj. 1. multilevel - of a building having more than one level signaling mode with no additional coding overhead (0 percent overhead), making it 25 percent more bandwidth efficient than typical 8B/10B coded transceivers. As with all Accelerant PAM4 transceivers, the AN6420 features adaptive equalization A transmission technique that dynamically adjusts its modulation method based on the quality of the line. performed by the part. For interoperation in legacy binary modes with SERDES on existing line cards, the AN6420 operates up to 5 Gb/s with a Decision Feedback Equalizer (DFE) in the receiver enabling it to offer robust operation independent of the quality of the legacy link.
For legacy upgrades the AN6420 includes the world's first binary backplane DFE implementation, allowing error-free operation at speeds up to 5Gb/s even with eyes that are completely closed. This insures interoperability with the binary SERDES typical of the installed base of system line cards, enabling greater opportunities for system developers to upgrade existing network, server, and system chassis backplanes to higher performance.
"Maintaining a reasonable power budget, operating over low-cost interconnects, and interoperating with existing hardware have been the primary obstacles to upgrading existing backplanes to higher speed performance," said Bill Hoppin, vice president of marketing for Accelerant. "System developers have now designed Accelerant's AN6000 series into strategic upgrade projects that result in fundamental changes to product lifecycle Product lifecycle or product life cycle is the course of a product's sales and profits over time. The five stages of each product lifecycle are product development, introduction, growth, maturity and decline. at the system level. In addition, the technology is available now in an ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. flow that provides the same functionality and power advantages of the discrete AN6420."
Many system vendors depend on ASIC integration to create key differentiation. Typically, technology available in the form of discrete merchant ICs has outpaced that available in ASIC cores by at least a generation. In backplane SERDES technology, power per user Gigabit is the ultimate metric when integrated as an ASIC core. The availability of Accelerant's leading edge, low power-per-user Gb/s technology both as a discrete IC and in an ASIC flow simultaneously is significant, as system developers will have greater design flexibility and cost-effectiveness both for today's upgrades and for tomorrow's next generation system designs.
The AN6420 is built with Accelerant's new modular development architecture such that each building block can be re-used and optimized for custom applications and integration into ASIC designs. Power consumption and die size of each building block are extremely low, and are optimized for either backplane interconnect or chip-to-chip applications. The 130nm AN6420 core is available today from Agere Systems in its ASIC flow. Accelerant's building blocks are also ideal for future cores integrated on 90nm CMOS (Complementary Metal Oxide Semiconductor) Pronounced "c-moss." The most widely used integrated circuit design. It is found in almost every electronic product from handheld devices to mainframes. optimized for further improvements in die density and low power.
Pricing and Availability
The AN6420 is a 17mm X 17mm low cost plastic BGA (Ball Grid Array) A popular surface mount chip package that uses a grid of solder balls as its connectors. Available in plastic and ceramic varieties, BGA is noted for its compact size, high lead count and low inductance, which allows lower voltages to be used. device, is sampling now, and is priced at $80 per unit in volume.
Accelerant Networks is a fabless semiconductor company A fabless semiconductor company specializes in the design and sale of hardware devices implemented on semiconductor chips. It achieves an advantage by outsourcing the fabrication of the devices to a specialized semiconductor manufacturer called a semiconductor foundry or "fab. delivering intelligent silicon transceivers that unlock new levels of bandwidth from low-cost interconnects such as backplanes and cables used commonly in the network, storage and server markets. The company is headquartered in Beaverton, Ore., with sales and application offices in Silicon Valley as well as a nationwide network of sales representatives. For more information visit Accelerant on the web at www.accelerant.net.
This release is available online at: http://www.accelerant.net/news_events/releases/20031027.htm.