AccelChip Raises $6.652 Million in Series B Funding; Investors See Value in Algorithm-to-Hardware Solution for the DSP Market.Business Editors MILPITAS, Calif.--(BUSINESS WIRE)--May 5, 2003 AccelChip Inc., the leading provider of high-level synthesis tools for DSP (1) (Digital Signal Processor) A special-purpose CPU used for digital signal processing applications (see definition #2 below). It provides ultra-fast instruction sequences, such as shift and add, and multiply and add, which are commonly used in math-intensive design, today announced the closing of its second round of funding in the amount of $6.652 million. The Series B round was led by InterWest Partners with participation from Greylock Partners, Xilinx, Arch Development Arch Development, a rock band from Richmond, Virginia, was formed in 2005 by lead guitarist Spencer "ViE" Bonnevie, and bassist Chris Thomas. Soon after, guitarist Blake Cotton joined their group. Their positions for drummer and lead singer are undecided as of late. Partners, and several private investors. Since its introduction in September of 2002, AccelChip's AccelFPGA high-level synthesis tool has been adopted by DSP algorithm developers worldwide in the defense, communications, transportation and consumer markets to address a critical productivity barrier in the DSP design process. AccelFPGA is the only EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. tool that synthesizes the MATLAB (MATrix LABoratory) A programming language for technical computing from The MathWorks, Natick, MA (www.mathworks.com). Used for a wide variety of scientific and engineering calculations, especially for automatic control and signal processing, MATLAB runs on Windows, Mac and (R) language, which is used by the overwhelming majority of DSP designers for modeling and analysis of DSP algorithms. AccelFPGA synthesizes MATLAB designs, automating the creation of synthesizable RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; models and simulation testbenches compatible with all FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market. design flows and creating the industry's first bridge between the DSP and FPGA design environments. By enabling a true top-down DSP design process, AccelChip allows DSP algorithm developers to realize FPGA implementations quickly and reliably, shaving months off the traditional manual design cycle. "FPGAs are increasingly proving to be the best hardware implementation choice for high-performance DSP algorithms, and yet few if any commercial EDA solutions exist that link the disparate DSP and FPGA design worlds," said AccelChip CEO (1) (Chief Executive Officer) The highest individual in command of an organization. Typically the president of the company, the CEO reports to the Chairman of the Board. and EDA veteran Dan Ganousis. "We've staked a claim to that territory by delivering the first high-level synthesis tool for the MATLAB language, and are pleased at the support we've garnered from the investment community and our strategic partners." AccelChip will use its new capital to expand its product development group, which is located in Lake Oswego Lake Os·we·go A city of northwest Oregon, a residential suburb of Portland. Population: 35,800. , Ore. and is headed by CTO (Chief Technical Officer) The executive responsible for the technical direction of an organization. See CIO and salary survey. and synthesis expert Michael Bohm. The funds will also be used to develop a marketing organization, expand AccelChip's sales force internationally under the leadership of Rick Carlson, former vice president of sales at Synplicity, and establish a consulting services group to service and support AccelChip's customers worldwide. "We are excited about AccelChip because their products solve a crucial market need using innovative technology," said Victor Westerlind, InterWest principal. "Look around and you will notice digital signal processing See DSP. Digital Signal Processing - (DSP) Computer manipulation of analog signals (commonly sound or image) which have been converted to digital form (sampled). applications everywhere. Signal processing See DSP. has taken off and FPGA's are becoming the platform of choice, creating a high growth market for AccelChip's DSP design tools." "As a seed and pre-seed venture fund we are very pleased that after leading the initial funding of this technology from its inception at Northwestern University, we were able to staff a truly outstanding management team that has successfully launched the company," said Robert A. Schriesheim, Managing General Partner at Arch Development Partners. "The new investment group represents a combination of the very best strategic partner - Xilinx - with experienced EDA venture investors led by Interwest and Greylock. This high quality group of investors will undoubtedly provide invaluable leadership for the company." AccelChip recently relocated its company headquarters to Milpitas, Calif. from Schaumburg, Ill. to facilitate closer working relationships with its strategic partners in the EDA, DSP and FPGA markets. About AccelChip AccelChip Inc., founded in 2000 and headquartered in Milpitas, Calif., develops and markets design tools that enable true, top-down DSP design. AccelChip's radically different EDA solutions provide the industry's first link from DSP to FPGA design environments, taking DSP algorithm developers from MATLAB to FPGA implementation automatically. For more information, visit the AccelChip Web site at www.accelchip.com or call (408) 943-0622. More information about the investors can be found at www.interwest.com, www.greylock.com, www.archdevelopmentpartners.com, and www.xilinx.com. |
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