AccelChip Inc. Improves Quality of Results and Furthers Integration with Key Industry Partners.SANTA CLARA Santa Clara, city, Cuba Santa Clara (sän`tä klä`rä), city (1994 est. pop. 217,000), capital of Villa Clara prov., central Cuba. , Calif. -- (Global Signal Processing See DSP. Exposition) AccelChip Inc., the industry's only provider of automated flows from MATLAB (MATrix LABoratory) A programming language for technical computing from The MathWorks, Natick, MA (www.mathworks.com). Used for a wide variety of scientific and engineering calculations, especially for automatic control and signal processing, MATLAB runs on Windows, Mac and (R) algorithms to silicon, today announced increased functionality for the company's AccelChip(R) DSP (1) (Digital Signal Processor) A special-purpose CPU used for digital signal processing applications (see definition #2 below). It provides ultra-fast instruction sequences, such as shift and add, and multiply and add, which are commonly used in math-intensive Synthesis product, plus new support for third-party partners' RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; synthesis and simulation tools. AccelChip DSP Synthesis accelerates the execution of MATLAB algorithms directly into FPGAs and ASICs by providing automatic implementation and verification flows for DSP algorithms. The tool's latest release, version 2004.5, includes support for new FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market. devices, enhanced flows for ASICs, and improved quality of results (QoR). "With the 2004.5 enhancements, AccelChip extends our DSP synthesis to more complex designs where a language-based flow is essential for compact and efficient algorithm development," said Michael Bohm, CTO (Chief Technical Officer) The executive responsible for the technical direction of an organization. See CIO and salary survey. and vice president of Engineering, AccelChip. "With the new release, we are targeting advanced array-based designs, such as those found in image processing image processing Set of computational techniques for analyzing, enhancing, compressing, and reconstructing images. Its main components are importing, in which an image is captured through scanning or digital photography; analysis and manipulation of the image, accomplished , radar, sonar, and real time communication, with new functionality that on specific designs decreases area up to 50% and increases sample rates by 10x over previous releases." Enhancements Provide Improved Quality of Results AccelChip DSP Synthesis allows designers to explore multiple micro-architectures and fixed-point representations without ever touching their golden MATLAB source -- increasing efficiency and providing unheard of flexibility. The tool's enhanced floating- to fixed-point conversion and enhanced scheduler provide the designer much better control over trade-offs between throughput, performance, area, and accuracy. By reducing the size of HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. arrays and automatically removing unreachable code, users of the new 2004.5 version will see an improvement in the QoR in their target silicon. Users can now also take advantage of the new implicit loop unrolling (ILU) functionality, another example of the leadership role AccelChip is taking in the algorithmic-based market. With ILU, AccelChip extends the common explicit loop unrolling, such as "for loops" that are found in other algorithmic tools, to array operations, where the user can specify all or down to the specific type of array to be unrolled; for example, array add, array subtract, array multiply, and matrix multiply. The enhanced scheduler optimization allows the user to combine the current stage with a previous stage before the loop, which results in increased sample rate. For example, in designs with ten loops, the sample rate could be increased by as much as 10X. Third-Party Support Ensures Easy Adoption in Current Design Flows AccelChip DSP Synthesis is designed to fit into current design flows and bridge the gap between MATLAB and RTL. With this release, it offers an integrated verification and implementation flow with any combination of the following products: --Aldec Riviera(TM) 2004.08 --Altera Quartus(R) II 4.1, Stratix II(TM), and Cyclone(TM) --Mentor Graphics Precision(R) RTL 2004a.75, LeonardoSpectrum(TM) 2004a-63, and ModelSim(R) 6.0 --Synopsys Design Compiler(R) 2004.06 -SP1 Design Compiler FPGA 2004.06-2 --Synplicity Synplify(R) Pro 7.6.1 --The MathWork's MATLAB 7 and Simulink(R) 6.0 --Xilinx ISE Ise (ē`sā), city (1990 pop. 104,164), Mie prefecture, S Honshu, Japan, on Ise Bay. It is one of the foremost religious centers of Shinto, the site of the shrines of Ise. 6.02.03i and Spartan(TM)-3 "The intuitive MATLAB user interface, its built-in math and graphics functions, and its powerful programming language make MATLAB the most popular, productive, and accurate DSP design environment today," said Jim Tung, MathWorks Fellow at The MathWorks, Inc. "The combination of AccelChip's 2004.5 release and our new MATLAB 7 provides our mutual customers with a direct path to FPGA and ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. implementations of DSP algorithms." Faster Time to Productivity AccelChip DSP Synthesis now contains 25 new design examples that allow users to quickly learn about the synthesizable MATLAB coding style and become proficient with the tool. Design examples range from basic mathematical operations, matrix operations, and complex numbers to complex examples for general signal processing (filters and transforms) and communications designs (convolution convolution /con·vo·lu·tion/ (-loo´shun) a tortuous irregularity or elevation caused by the infolding of a structure upon itself. , interleaving interleaving - sector interleave , down-conversion, and up-conversion). Availability AccelChip DSP Synthesis, version 2004.5, is available immediately. Current AccelChip customers, on support, will receive the new release at no additional fee. For more information on AccelChip DSP Synthesis and AccelWare IP, please email sales@accelchip.com or visit www.accelchip.com/sales.html. About the Company AccelChip Inc. develops and markets a MATLAB-based algorithmic synthesis environment and intellectual property that automate the development and implementation of DSP designs. The company's unique DSP Design Automation (DDA DDA Disability Discrimination Act (1995, UK) DDA Downtown Development Authority DDA Doha Development Agenda DDA Delhi Development Authority DDA Department for Disarmament Affairs DDA Demand Deposit Account DDA Domain Defined Attribute ) solutions reduce design iterations, accelerate the creation and verification of register-transfer language (RTL), and link the domain-specific DSP design environment with industry-standard hardware design flows targeting FPGAs and ASICs. Founded in 2000, AccelChip is located in Milpitas, California, and has design centers in Portland, Oregon, and Carlsbad, California. AccelChip's Web address is www.accelchip.com. AccelChip and AccelWare are registered trademarks of AccelChip Inc. All other trade names referenced are the service marks, trademarks, or registered trademarks of their respective companies. |
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