AccelChip Inc. Extends Leadership in Algorithmic Synthesis with New IP.

SAN FRANCISCO -- -- New AccelWare IP for Linear Algebra and Integration of MATLAB- and Simulink-based Synthesis Accelerate DSP Design --

AccelChip Inc., a leading provider of embedded DSP technology for accelerating design, today announced its 2005.1 release of AccelWare(R) intellectual property (IP) toolkits and AccelChip(R) DSP Synthesis product. New AccelWare cores extend the company's leadership position in cores that directly implement matrix operations for wireless communications, signal processing, and other forward-error correction applications. Additionally, the 2005.1 version of the AccelChip DSP Synthesis tool integrates the industry-leading, algorithmic synthesis environment based on MATLAB with Xilinx (NASDAQ: XLNX) System Generator, the industry-leading synthesis product based on Simulink. (For further information, see "Xilinx and AccelChip Deliver Industry's First Design Flow from MATLAB/Simulink and System Generator to Verified FPGA System," dated March 8, 2005.)

AccelWare DSP IP cores produce the industry's only fixed-point, hardware implementations of matrix inversion and matrix factorization. Building upon its recent release of QR factorization and inversion cores, AccelChip has added Cholesky matrix factorization and matrix inversion to its IP products. Matrix factorization and inversion are used with algorithms utilizing linear algebra techniques, for example, adaptive filters which are used in a wide range of applications from radar to global positioning systems.

The 2005.1 release also features new and enhanced cores that are fundamental to the development of Software Defined Radio (SDR), Digital Video Broadcasting, and other wireless communication applications. New cores support BCH decoding, BCH encoding, scrambling, and descrambling. This release also features additional micro-architecture configurations for the existing AccelWare FFT, IFFT, and filters cores. These new offerings are added to AccelChip's existing AccelWare toolkits--Building Block, Advanced Math, Communications, and Signal Processing.

"IP is an absolute requirement for algorithm development and implementation in DSP," said Michael Bohm, CTO and vice president of Engineering, AccelChip. "Virtually every DSP design we see can take advantage of cores to accelerate their development. Our AccelWare toolkits include more than 50 AccelWare IP cores with over 110 unique micro-architectures that are parameterized, reusable, and retargetable. Using the combination of application-specific cores with AccelChip algorithmic synthesis, our customers find they require minimal modification to their MATLAB and obtain optimized hardware more quickly than with alternative methods."

QR and Cholesky Matrix Factorization and Inversion

Being able to select from among multiple micro-architectures for blocks like matrix inversion and factorization is important in achieving an optimum solution for a specific application. QR provides a general factorization method for square and rectangular matrices without any symmetry restrictions. While more processing-intensive than Cholesky factorization, this method achieves more accurate numerical precision. Typical applications for the QR approach include adaptive recursive filtering, channel estimation and equalization, beam-forming, and image encoding algorithms. In contrast, Cholesky factorization requires less processing and hardware resources than QR because it takes advantage of the symmetry properties of the input matrix. Typical applications for the Cholesky approach include parameter estimation and speech coding algorithms.

2005.1 Provides Direct Path to Xilinx System Generator

As the result of joint development with Xilinx, AccelChip DSP Synthesis 2005.1 now provides the industry's first MATLAB/Simulink design flow for implementation of high performance DSP systems in FPGAs. The new interface automatically generates a verified System Generator IP block from a floating-point MATLAB model, supporting both cycle-accurate Simulink simulation and RTL generation within the System Generator environment.

"The combination of AccelChip and AccelWare together with System Generator allows us to rapidly build a prototype system that spans multiple FPGAs. Our DSP algorithm was already implemented in MATLAB, and without this, we would have to handcraft black boxes in either VHDL or Verilog for blocks not currently available with System Generator," said Dale Kluesing, CTO of Photron Technologies. "By allowing designers to create their own algorithms in MATLAB, explore various implementations using AccelWare, and then incorporate the blocks seamlessly into the rest of the system, this new flow dramatically reduces our design time."

Synthesis Extends Design Space Exploration

A great asset of architectural synthesis is the ability to rapidly generate multiple hardware implementations of a design from an algorithm. While traditional RTL synthesis tools have allowed area and frequency tradeoffs, AccelChip DSP Synthesis enables system-level tradeoffs, such as sample rate, latency, error, power, area and frequency. The 2005.1 release expands on the number of possible solutions by graphically enabling users to insert pipeline stages on critical paths. The synthesis engine will then balance the data paths to ensure correct behavior. In addition, direct memory mapping of two-dimensional MATLAB arrays is now supported for target architectures that have dual port or single port RAMs and ROMs.

Pricing and Availability

Version 2005.1 of AccelChip DSP Synthesis and AccelWare IP Toolkits is now shipping. Current AccelChip customers on support will receive the new release at no additional fee. The System Generator Interface is a new option to AccelChip DSP Synthesis and starts at $1000. For more information on AccelChip DSP Synthesis and AccelWare IP, please email [e-mail].

About the Company

AccelChip Inc. is the industry's only provider of MATLAB-based algorithmic synthesis solutions, including DSP intellectual property (IP), for embedded DSP design. The company develops and markets design tools, integrated verification flows, and parametric IP toolkits that combine to automate the development and implementation of DSP algorithms in FPGAs and ASICs. AccelChip's proven solution integrates the domain-specific DSP design environment (MATLAB) with industry-standard hardware design flows from Aldec, Altera, Cadence, Mentor Graphics, Synplicity, Synopsys, The MathWorks, and Xilinx. Founded in 2000, AccelChip is located in Milpitas, California, and has design centers in Portland, Oregon, and Carlsbad, California. AccelChip's Web address is www.accelchip.com.

AccelChip, AccelWare, and AccelView are registered trademarks of AccelChip Inc. All other trade names referenced are the service marks, trademarks, or registered trademarks of their respective companies.