AccelChip Inc. Achieves New Level of Array- and Matrix-based Algorithmic Synthesis.

MILPITAS, Calif. -- AccelChip DSP Synthesis 2004.6 includes Industry's First Matrix Inversion and Factorization Intellectual Property for DSP Design

AccelChip Inc., a leading provider of embedded DSP technology for accelerating FPGA and ASIC design, today announced significant new MATLAB(R) language support that improves the ability to create forward-error correction algorithms written in MATLAB for synthesis and verification in its AccelChip(R) DSP Synthesis product. AccelChip DSP Synthesis version 2004.6 also extends its device and third-party tool integration with new support for Cadence's Incisive(TM) Simulator and Xilinx's (Nasdaq:XLNX) Virtex-4(TM) devices. In conjunction with 2004.6, the company is introducing a unique AccelWare(R) fixed-point intellectual property (IP) toolkit that includes cores for inversion and factorization of two-dimensional arrays. This new toolkit, together with AccelChip DSP synthesis, extends the AccelChip solution into wireless communications and other forward-error correction applications, such as beamforming, Kalman filtering, and global satellite positioning.

To provide uninterrupted video and audio signals, digital communication devices make use of Reed-Solomon encoders and decoders, which use a common, block-based, error-correcting algorithm. Most Reed-Solomon designs are based on a specialized area of mathematics known as binary Galois fields. In hardware implementation, the use of Galois fields greatly reduces the amount of hardware required, while increasing the performance. Designers using advanced coding techniques in communications and encryption applications will benefit from the new native support for Galois fields provided in AccelChip DSP Synthesis 2004.6.

"In the absence of development systems that support Galois functions, such as AccelChip DSP Synthesis, designers are forced to use logarithms to perform multiplication on finite fields. This implementation severely limits the performance of Reed-Solomon decoders," said Michael Bohm, CTO and vice president of Engineering, AccelChip. "With the 2004.6 release of AccelChip DSP Synthesis, MATLAB algorithms that take advantage of binary Galois fields can now be synthesized directly to FPGA and ASIC hardware, resulting in faster and smaller implementations."

AccelChip Strengthens Design Verification Flow

AccelChip DSP Synthesis bridges the gap between algorithmic development and traditional RTL design flows. Through the Cadence Connections program, AccelChip's verification flow for ASIC design has been extended through the integration of Cadence Design System's Incisive Unified Simulator.

"Advanced DSP design requires high-performance system verification at multiple levels of abstraction," said Mitch Weaver, vice president and general manager, Systems and Functional Verification Division at Cadence Design Systems. "The Cadence Incisive functional verification platform provides a complete verification solution at all levels of design abstraction from architectural specification down to gate-level implementation. This collaboration with AccelChip will help optimize the design chain and accelerate the time to market for our mutual DSP customers."

AccelChip Enhances Tool to Support New Xilinx Virtex-4 Device

To take full advantage of the target FPGA's built-in resource such as RAMs, ROMs, multipliers, and MACs, AccelChip DSP Synthesis employs a proprietary resource description language (RDL), which ensures the VHDL and Verilog being produced maps directly to the device's unique building blocks. The 2004.6 release adds initial RDL support for the Virtex-4 architecture. Future releases will continue to optimize the powerful new Virtex-4 device.

"AccelChip DSP Synthesis is designed to be target-technology aware. This enables it to harness the power of the building blocks available within the target device. By developing a unique RDL for the Virtex-4, our AccelWare IP and customer designs can easily retarget to and take advantage of the new DSP-48 blocks without requiring any code modifications, thus making the design and IP truly portable," Bohm continued.

"Wireless communications require high-speed performance and flexibility," said David Squires, marketing director of the DSP Division at Xilinx. "Our Virtex-4 devices have the highest performance, lowest power, and are the most cost-effective FPGAs available for wireless networking applications. AccelChip DSP Synthesis, a powerful design tool that provides a direct link between the MATLAB language and our products, enables a simpler design paradigm by allowing designers to use MATLAB M-files as the golden design source."

New Toolkit Includes Reusable/Retargetable Matrix Inversion/Factorization Cores

AccelChip has added an Advanced Math Toolkit to its AccelWare IP. This offering includes the industry's first tool that produces fixed-point, hardware implementations of matrix inversion and matrix factorization using QR decomposition techniques. AccelWare cores are reusable and retargetable IP that enable MATLAB architectural synthesis of FPGAs and ASICs. The cores use proprietary resource-mapping technology to achieve the highest quality of results. AccelChip currently offers four toolkits to accelerate design creation and implementation, including Building Block, Signal Processing, Communications, and now, Advanced Math toolkits.

The 2004.6 release provides a total of four new AccelWare cores and an additional ten cores with new micro-architectures, including a Viterbi decoder, a Reed-Solomon decoder, polyphase decimation filters with programmable coefficients, and various micro-architectures, including radix-4 FFT/IFFT and FIR filters. In all, AccelChip provides more than 40 commonly used DSP cores and includes 108 micro-architectures targeted for DSP applications in consumer, communications, defense, and transportation industries. All blocks are vendor and technology neutral, allowing code portability which provides easy migration between device families.

"AccelChip believes IP to be a key enabler of architectural synthesis. In contrast, C-based implementation flows may require costly and error-prone, low-level design of DSP building blocks such as FFTs that must be specified in detail by experts. AccelWare IP facilitates rapid design exploration and implementation, while enabling the design team to keep its golden MATLAB source at a high level of abstraction, a major benefit of architectural synthesis," Bohm continued.

Availability

AccelChip DSP Synthesis, version 2004.6, is now shipping. Current AccelChip customers, on support, will receive the new release at no additional fee. For more information on AccelChip DSP Synthesis and AccelWare IP, please email [e-mail].

About the Cadence Connections Program

The Cadence Connections program promotes open interoperability in all areas of electronic design, including digital, custom IC, analog/mixed-signal, and PCB design. By attracting best-in-class members, Cadence offers the industry's largest collection of third-party solutions operating fully with the Cadence suite of design tools. The Connections program has over 120 member companies working toward developing an optimized silicon design chain for customers. Information about the Connections program may be found at http://www.cadence.com/partners/connections/.

About the Company

AccelChip Inc. is the industry's only provider of MATLAB-based algorithmic synthesis solutions, including DSP intellectual property (IP), for embedded DSP design. The company develops and markets design tools, integrated verification flows, and parametric IP toolkits that combine to automate the development and implementation of DSP algorithms in FPGAs and ASICs. AccelChip's proven solution integrates the domain-specific DSP design environment (MATLAB) with industry-standard hardware design flows from Aldec, Altera, Cadence, Mentor Graphics, Synplicity, Synopsys, The MathWorks, and Xilinx. Founded in 2000, AccelChip is located in Milpitas, California, and has design centers in Portland, Oregon, and Carlsbad, California. AccelChip's Web address is www.accelchip.com.

AccelChip, AccelWare, and AccelView are registered trademarks of AccelChip Inc. All other trade names referenced are the service marks, trademarks, or registered trademarks of their respective companies.