AccelChip Inc. Accelerates Digital Wireless Communication and Signal Processing Design with New Intellectual Property.

SANTA CLARA, Calif. -- AccelChip Inc., the industry's only provider of automated flows from MATLAB(R) algorithms to silicon, today announced that it has extended its AccelWare(R) Intellectual Property (IP) libraries to include key building blocks for signal processing and communication applications. This new IP enables the acceleration of algorithms running on standard DSP and embedded processors by 10-100x.

AccelWare is parametric IP that provides a direct path to hardware implementation of complex MATLAB toolbox and built-in functions. The new AccelWare blocks extend the range of the existing AccelChip(R) DSP Synthesis toolset into various real-time, continuous communications and array signal-processing systems, including space-time adaptive processing, wireless signal processing, software-defined radio, global positioning, radar, and sonar. Acceleration of both standard and embedded DSP processors is becoming a key requirement of these next-generation systems, and AccelChip Inc. is working with leading semiconductor vendors to enhance these types of communications designs.

"Wireless communication continues to be the dominant application for traditional DSP design," said Will Strauss, president of Forward Concepts, the premier market research organization tracking DSP trends. "To achieve system requirements, future high-performance communications systems are going to be a combination of software running on programmable or embedded DSP processor(s) plus dedicated hardware to accelerate key aspects of the algorithms in the system."

The combination of AccelWare IP with AccelChip DSP Synthesis provides a high level of reuse and portability, allowing designers to migrate existing designs faster. AccelChip's toolset and IP can also be used to design entire DSP systems or to develop DSP accelerators. A DSP accelerator is a high-speed FPGA or ASIC that interfaces with a DSP processor bus. It is designed to accelerate portions of the overall algorithm in order to achieve a high-performance system.

"The technology drive toward higher bandwidths, increased resolution, and maximum precision are all combining to cause the processor to reach its natural sequential limitations," said Michael Bohm, CTO and vice president of Engineering, AccelChip. "By creating hardware implementations of key aspects of the algorithms, designers are more likely to meet pre-design performance expectations. Our new AccelWare IP enables the rapid development of accelerators that move key algorithms to hardware to enhance system performance and increase throughput."

AccelWare's Multiple Micro-architectures Facilitate Designs Optimized For Specific Markets

In an industry that traditionally offers general-purpose IP where only bit widths can be changed, AccelWare's fully parameterized IP provides multiple micro-architectures, or configurations, that enable the blocks to be tailored for specific market application needs, such as throughput, latency, noise, power, frequency, or area. Additionally, the micro-architectures utilize the company's proprietary resource-mapping technology to achieve high quality of results on targeted FPGA architectures.

AccelWare's DSP-oriented IP corresponds to The MathWorks' communication and signal processing toolboxes. Because AccelWare modules generate MATLAB, they are at a higher level of abstraction than traditional netlist or RTL-based (register-transfer level) IP. This enables a greater degree of architectural exploration and market-specific customization, significantly expanding the range of target applications.

The additions to the AccelWare IP include parameterized models for a Viterbi decoder, Galois field operators, polyphase decimation filters with programmable coefficients, radix-4 FFTs and IFFTs, and FIR filter serial-distributed arithmetic (SDA) and parallel-distributed arithmetic (PDA) architectures.

Availability

AccelWare IP libraries are available immediately. Current AccelWare customers, on support, will receive the models at no additional fee. For more information on AccelChip DSP Synthesis and AccelWare IP, please email [e-mail] or visit www.accelchip.com/sales.html.

About the Company

AccelChip Inc. develops and markets a MATLAB-based algorithmic synthesis environment and intellectual property that automate the development and implementation of DSP designs. The company's unique DSP Design Automation (DDA) solutions reduce design iterations, accelerate the creation and verification of register-transfer language (RTL), and link the domain-specific DSP design environment with industry-standard hardware design flows targeting FPGAs and ASICs. Founded in 2000, AccelChip is located in Milpitas, California, and has design centers in Portland, Oregon, and Carlsbad, California. AccelChip's Web address is www.accelchip.com.

Technical Information on the IP Blocks

The AccelWare Viterbi model supports two micro-architectures: CSA (compare-select-add) and ACS (add-compare-select). The AccelWare Viterbi decoder is designed to support the OC-3 data rates using the CSA architecture. For designs not requiring OC-3 data rates, the more area-efficient ACS architecture consumes about 30% less area than the CSA architecture. Both architectures use familiar MATLAB parameters such as constraint length, code generators, traceback length, and the number of soft decision bits. All options are available from AccelWare's easy-to-use user interface. In addition, the AccelWare Viterbi decoder supports punctured codes for implementing higher rate decoders.

The AccelWare polyphase decimation filter supports the following micro-architectures: transposed/non-resource shared architecture, direct/resource shared architecture, and transposed/reduced memory architecture. The direct micro-architecture supports hardware resource sharing among polyphase sub-filters, plus an optional capability to define programmable/loadable filter coefficients.

The AccelWare FIR filter supports the following micro-architectures: direct form, transposed form, parallel distributed architecture (PDA), and serial distributed architecture (SDA). The PDA and SDA micro-architectures are highly efficient LUT-based implementations. The PDA micro-architecture provides for high speed (greater than 250MHz) implementations, while the SDA micro-architecture provides a minimum resource implementation for area efficiency. The transposed and direct-form micro-architectures provide traditional FIR filter implementation options for systems targeting ASICs, with the additional option to resource-share for area efficiency.

The AccelWare FFT/IFFT supports two micro-architectures: logarithmic base of the FFT/IFFT (radix-2 or radix-4) and the decimation algorithm in either time or frequency. In addition, the user has the option to pipeline the butterfly/dragonfly to achieve high throughput (greater than 160MHz). The AccelWare FFT/IFFT is designed using a minimum resource implementation -- a single butterfly/dragonfly is resource-shared to implement an N-point FFT/IFFT. The internal memory structure is optimized to minimize RAM/ROM utilization.