AccelChip Inc.'s New AccelWare DSP Libraries Deliver on Promise of IP; Bring Seamless Flow/Flexibility to FPGA, ASIC, and Structured ASIC Development Process.

Business Editors/High-Tech Writers

MILPITAS, Calif.--(BUSINESS WIRE)--March 1, 2004

AccelChip Inc., the industry's only provider of automated flows from MATLAB(R) algorithms to silicon, today announced AccelWare(R) DSP Libraries, a set of synthesizable, verified, fixed-point, digital signal processing (DSP) building blocks that enable a true, top-down MATLAB-to-silicon synthesis and verification flow for FPGA, ASIC, and structured ASIC design.

Intellectual Property (IP) can reduce time to market by eliminating the need to design commonly used functions, such as filters, FFTs and encoders/decoders. However, design teams are still forced to manually convert floating-point algorithms to fixed-point models, then recapture the entire design in other systems and languages, leaving major holes in verification, and extending the design cycle by months.

The new AccelWare libraries unlock the design from device-specific IP limitations found in vendor-provided tools. AccelWare modules generate hardware-oriented IP at a higher level of abstraction than netlist or RTL-based (register-transfer level) IP. This enables a greater degree of core customization, and greatly expands the range of target applications. Customization may also improve hardware by reducing the need to design around or include an IP block with sub-optimal specifications.

"AccelWare DSP Libraries deliver on the promise of IP for DSP design by making more effective use of language-based design flow," said Tom Feist, vice president of Sales & Marketing, AccelChip. "By using AccelWare's parameterized behavioral DSP block libraries during the algorithm development stage of their design, algorithm developers, systems designers and ASIC/FPGA designers can all work off one golden MATLAB model, and are able to rapidly make architectural trade-offs for area, speed and power."

The current path from DSP algorithm development to implementation is time consuming and limited. Engineers typically recapture their design using a graphical modeling environment or a general-purpose language, such as C/C++ or VHDL/Verilog. AccelWare's parameterized, DSP-oriented MATLAB functions correspond to The MathWorks' communication and signal processing toolboxes. These new libraries enable companies to use one golden source for their entire design process, allowing developers to remain in their preferred MATLAB development environment.

"With the DSP market's expected growth rate of 23% through 2007, and designs already outpacing the fastest off-the-shelf DSPs, alternative design solutions are needed now," said Will Strauss, president of Forward Concepts, the premier market research organization tracking DSP trends. "As far as I know, AccelChip is the only company providing an effective MATLAB-based approach to the problem."

AccelWare Provides Direct Path to Implementation of MATLAB

Functions

Over time, the MATLAB language has grown to include callable functions to perform common signal processing and mathematical calculations. Many of these simulation functions are provided through The MathWorks toolboxes. When used in conjunction with AccelChip(R) DSP Synthesis tools, AccelWare libraries provide a direct path to implementation for many of these functions. It also provides integration into The MathWorks' Simulink(R) tool for system simulation and integration into Xilinx (Nasdaq:XLNX) System Generator flows.

Simulink, a system-level design and simulation environment, is becoming a common part of system-level verification for ASICs and FPGAs being developed for DSP applications. Simulink provides a cycle-accurate system verification environment for DSP design by providing a sample-based simulation environment that more closely represents the behavior of the actual hardware.

AccelChip DSP Synthesis tools provide a highly efficient method for creating algorithmic functions not provided as standard Simulink blocks. Through AccelChip's Export Simulink functionality, these functions can be easily incorporated into larger system-level Simulink simulations. AccelWare libraries include the ability to export the fixed-point MATLAB model to Simulink with latency and throughput information as determined by the hardware-generation process. RTL generated by AccelWare library blocks can be used with standard ASIC and FPGA flows.

The AccelWare library builds on optimized DSP models provided by Bit-tru, a DSP IP company acquired by AccelChip Inc. in October of 2003. AccelWare includes a library of parameterized and synthesizable IP cores that can be included into designs being developed for implementation through AccelChip DSP Synthesis tools. (See "AccelChip Inc.'s New DSP Synthesis Tool Decreases DSP Design Costs," dated March 1, 2004.)

Availability

AccelWare DSP Libraries are available immediately. For pricing on any of the AccelWare DSP libraries, please email [e-mail], or visit www.accelchip.com/sales.html.

About the Company

AccelChip Inc., founded in 2000 and headquartered in Milpitas, California, develops and markets design tools, intellectual property and consulting services that enable a true, top-down DSP design process. AccelChip's innovative electronic design automation solutions link the domain-specific DSP design environment with proven silicon design flows, allowing DSP algorithm developers to go directly from MATLAB to silicon implementation with high-quality results. AccelChip's Web address is www.accelchip.com.

AccelChip and AccelWare are registered trademarks of AccelChip Inc. All other trade names referenced are the service marks, trademarks, or registered trademarks of their respective companies.