AccelChip Inc.'s Enhanced DSP Synthesis Tool Decreases DSP Design Costs; Accelerates Time to Market.

Business Editors/High-Tech Writers

MILPITAS, Calif.--(BUSINESS WIRE)--March 1, 2004

AccelChip Inc., the industry's only provider of automated flows from MATLAB(R) algorithms to silicon, today announced the next generation of its digital signal processing (DSP) synthesis tools. The new AccelChip(R) DSP Synthesis tool accelerates the ASIC and FPGA development process by providing automatic implementation and verification flow for DSP algorithms. DSP algorithms are commonly used in communications, military/aerospace, and automotive applications.

Prior to AccelChip's entry into the market in 2002, DSP algorithm developers using a MATLAB-based flow did not have a direct flow to silicon. AccelFPGA was the industry's first commercial tool to generate synthesizable register-transfer language (RTL) code from MATLAB, the world's leading software for algorithm design. Thanks to AccelChip, DSP designers are now able to use the MATLAB design as the golden source for driving synthesis and verification.

The AccelChip DSP Synthesis tool provides expanded architectural exploration capabilities, including support for FPGA, ASIC, and structured ASIC; enhanced flows with The MathWorks' Simulink(R), Xilinx (Nasdaq:XLNX) ISE, and Xilinx System Generator tools; and support for AccelChip's new parameterized DSP libraries. These enhancements create a seamless flow between algorithm development and silicon implementation, and extend the company's DSP synthesis to more complex designs.

"Extreme time-to-market pressures are forcing design engineers to increase productivity without sacrificing quality. Companies can spend months trying to squeeze the last few nanoseconds at the physical level to meet design requirements," said Tom Feist, vice president of Sales and Marketing, AccelChip. "At the architectural level, the new AccelChip DSP Synthesis tool allows designers to trade off area, performance, and power where designs can be moved more than 100x. And now, with its links to Simulink and System Generator, algorithms can be easily integrated into the complete chip."

In previous design methodology, designs were locked down early in the cycle. Making architecture changes required multiple rewrites to code, test benches, and extensive verification back to MATLAB source models. AccelChip DSP Synthesis allows designers to explore possibilities without ever touching their golden source, increasing efficiency, and providing unheard-of flexibility. The tool's enhanced floating- to fixed-point conversion gives the designer much better control over trade-offs between performance, area and accuracy.

"With AccelChip's floating-point to fixed-point conversion, we were able to quickly select the exact number of bits needed to meet our allowable noise," said Jay Johnson, electrical engineering manager, Electro Scientific Industries, Inc. "The result was a sinc interpolation filter in a Xilinx FPGA that met our design requirements in about three hours, versus two weeks with our traditional RTL design flow."

The AccelChip DSP Synthesis tool, which generates cycle-accurate models for a DSP-based component integration environment such as Simulink, enables system-level verification of all components using libraries and math-based models. AccelChip DSP Synthesis exports simulation models that are verified against the golden MATLAB source into Simulink, enabling rapid system verification. AccelChip DSP Synthesis also works with System Generator, a system-level modeling tool that facilitates FPGA hardware design. This integration enables verification of AccelChip-generated modules with Xilinx's IP.

"The AccelChip DSP Synthesis tool complements MATLAB by providing a path to silicon implementation. Its interface to Simulink allows DSP designers to validate designs using Simulink to integrate components into a complete system model," said Jim Tung, MathWorks Fellow at The MathWorks. "This is an example of how tool vendors can take advantage of the open interfaces in MATLAB and Simulink for the benefit of DSP algorithm developers, as well as hardware designers."

An option to AccelChip DSP Synthesis also speeds development time: AccelWare(R) is a library of parameterized generators that produce performance-critical DSP components -- such as FIR filters, FFTs, and encoders/decoders -- directly from MATLAB. (See "AccelChip Inc.'s New AccelWare DSP Libraries Deliver on Promise of IP," dated March 1, 2004.)

Availability

AccelChip DSP Synthesis is available immediately. All existing AccelFPGA customers with an active support contract will receive an upgrade to AccelChip DSP Synthesis at no additional fee. For pricing on any of the AccelChip DSP Synthesis tools, please email [e-mail], or visit www.accelchip.com/sales.html.

About the Company

AccelChip Inc., founded in 2000 and headquartered in Milpitas, California, develops and markets design tools, intellectual property, and consulting services that enable a true, top-down DSP design process. AccelChip's innovative electronic design automation solutions link the domain-specific DSP design environment with proven silicon design flows, allowing DSP algorithm developers to go directly from MATLAB to silicon implementation with high-quality results. AccelChip's Web address is www.accelchip.com.

AccelChip and AccelWare are registered trademarks of AccelChip Inc. All other trade names referenced are the service marks, trademarks, or registered trademarks of their respective companies.