AccelChip, ChipX Announce Partnership to Automate IC Design Flows; Collaboration Gives Customers Complete Path from Algorithms to Silicon for Structured ASICs.

Business Editors/High-Tech Writers

Design Automation Conference 2004

MILPITAS, Calif.--(BUSINESS WIRE)--May 27, 2004

AccelChip Inc., the industry's only provider of automated flows from MATLAB(R) algorithms to silicon, announced today it is extending its AccelChip Silicon vendor Alliance Program (ASAP) through a partnership with ChipX, a leading manufacturer of Structured ASICs. Under terms of the agreement, AccelChip will enhance its AccelChip(R) DSP Synthesis tool to provide highly optimized results for ChipX's Structured ASIC products. When combined with AccelChip's AccelWare(R) DSP parametric libraries and industry-standard IC flow, designers targeting ChipX devices will now have a highly optimized, top-down, language-based flow for DSP design.

"DSP designers have always faced a significant challenge developing a faster, more efficient path from tools to final silicon," said Elie Massabki, vice president of Marketing for ChipX. "With this agreement, customers using AccelChip's tools and parametric libraries can easily retarget designs that have been prototyped in an FPGA into a Structured ASIC, providing an ideal economical solution for DSP design."

Over the past several years, the escalating cost of full custom, cell-based ASICs and the inherent performance limitations of FPGAs have driven designers to seek high performing, but more cost-effective alternatives. Designed to reduce the high NRE (non-recurring engineering) costs traditionally associated with cell-based approaches, Structured ASICs feature pre-configured patterns of logic cells, memory, and I/O. This architecture allows engineers to customize their logic during the application of the final few metal layers of the device, and, in the process, reduce NRE cost and shorten the development cycle.

AccelChip provides software and services that automate the path from DSP algorithms to silicon, accelerating the DSP design cycle and increasing the quality of results. Unlike other flows that require manual translation of MATLAB to proprietary C languages, graphical capture tools, or RTL (register-transfer-level), AccelChip products automate this flow while providing design exploration and a complete verification environment.

By extending this flow with device-specific optimizations, ASAP levels the playing field for all semiconductor vendors who cannot afford to invest millions in their own proprietary flow. The program achieves this goal by supporting industry-standard IC design flows based on RTL design methodology and by developing resource description models for program participants. Besides ChipX, current program participants include Altera, Elixent, and Xilinx.

"The DSP design market is performance critical, a tremendous advantage for the new Structured ASIC architecture vendors such as ChipX," said Dan Ganousis, president and CEO for AccelChip. "The combination of their silicon with AccelChip's automatic path from MATLAB to RTL will dramatically accelerate our mutual customers' algorithm-to-silicon design cycle."

AccelChip will demonstrate its DSP Synthesis tool featuring the ChipX Structured ASIC flow at the 41st Annual Design Automation Conference (DAC) in San Diego, California (June 7-11, 2004), booth 1539. A new version of AccelChip DSP Synthesis with support for ChipX's Structured ASIC products will be available in June 2004.

About the Companies

ChipX, formerly known as Chip Express, is a leading manufacturer of late-stage programmable application-specific integrated circuits, or structured ASICs. The company's innovative, patented technology consolidates wafer production tooling, reduces time-to-market, and minimizes the cost of initial production. ChipX Structured ASIC technology is widely used in automotive telematics, computing peripherals, communications, high-end consumer electronics, industrial control, medical equipment, and military/aerospace systems. For more information, please visit the company's website at www.chipx.com.

AccelChip Inc. develops and markets a MATLAB-based algorithmic synthesis environment, intellectual property, and consulting services that enable a true, top-down DSP design. AccelChip's unique DSP Design Automation (DDA) solutions link the domain-specific DSP design environment with industry-standard FPGA, ASIC, and structured ASIC design flows and are proven to dramatically accelerate the DSP design cycle and increase the quality of results. Founded in 2000, AccelChip is located in Milpitas, California, and has design centers in Portland, Oregon, and Carlsbad, California. AccelChip's Web address is www.accelchip.com.

AccelChip and AccelWare are registered trademarks of AccelChip Inc. All other trade names referenced are the service marks, trademarks, or registered trademarks of their respective companies.