AXYS Design Introduces Model for Infineon's Next Generation CARMEL DSP Core and Expands OEM Partnership With Mentor Graphics.

Business Editors/High-Tech Writers

DesignCon 2002

Booth No. 720

PALO ALTO, Calif.--(BUSINESS WIRE)--Jan. 29, 2002

AXYS(R) Design Automation, Inc. today announced a new model for Infineon Technologies' next generation CARMEL(TM) DSP Core with support from the Mentor Graphics(R) Seamless(R) co-verification environment to be available in the first quarter of 2002. The new CARMEL10xx+ model extends the existing CARMEL10xx model to support 2*CLIW Address Range and the Extended Shadow Registers of the CARMEL 20xx DSP family. The model is integrated with the TASKING CrossView Pro 3.0 and 2.0 debuggers and runs on Windows 32 and Unix platforms.

"Tools and models are very important for CARMEL DSP users. The Mentor Graphics Seamless co-verification environment and AXYS Design provide the right ingredients to enable embedded software development throughout the complete SoC design cycle from early architecture exploration in AXYS Design's MaxSim Developer Suite to final driver and firmware verification using Seamless co-verification," said Alex Bedarida, vice president of DSP at Infineon Technologies AG.

With the introduction of the Infineon CARMEL10xx+ model AXYS Design also reinforces its position as Mentor Graphics' largest independent supplier of Processor Support Packages (PSP) for the Seamless hardware/software co-verification environment. As a member of Mentor's Seamless Partner Program, AXYS Design now supplies, amongst others, PSPs for Infineon's CARMEL DSP and C166S-V2 processor architectures to Mentor. All models used in these PSPs have been produced using AXYS Design's MaxSim and MaxCore Developer Suites.

"AXYS Design has been a reliable partner to Mentor over the past several years. The PSPs provided by AXYS are amongst the best in performance and accuracy," commented Serge Leef, general manager of the Mentor Graphics SoC Verification Division. "We are pleased to now support Infineon's powerful RISC and DSP architectures."

Stefan Tamme, AXYS Design's vice president of marketing and sales explained, "We are excited to work with two industry leaders in the commercialization of these simulation models. We stand ready to support our joint customers and licensees with models and tools that help them getting the job done. Over the next several months we will further automate the generation of Seamless models from our MaxSim Developer Suite to enable the automatic generation of multi-core PSPs for use in Seamless."

About AXYS Design Automation, Inc.

AXYS Design Automation, Inc. is a provider of fast, accurate, and integrated processor and SoC (System-on-Chip) C/C++ modeling and simulation solutions for the development of high software content SoC devices. The use of AXYS Design's tool suites in the pre-silicon phase substantially shortens the SoC design cycle by enabling early system integration and embedded software development, thus reducing NRE cost and time to market.

The MaxSim(TM) Developer Suite is a tool enabling the modeling and verification of multi-core SoC designs. The MaxCore(TM) Developer Suite is a toolset for the automatic generation of processor models and software development tools. MaxLib(TM), AXYS Design's growing library of models for popular SoC components, currently includes processors from Conexant Systems (Nasdaq:CNXT), DSP Group (Nasdaq: DSPG), Infineon Technologies (NYSE:IFX)(FSE:IFX) and LSI Logic (NYSE: LSI). AXYS Design also offers cycle-callable/cycle-accurate models of ARM's (LSE:ARM)(Nasdaq:ARMHY) ARM 7 and ARM 9 architectures and MIPS Technologies' (Nasdaq:MIPS) MIPS32 and MIPS64 cores. For more information, visit the AXYS Design web site at www.AXYSdesign.com.

Note to Editors: AXYS(R) is a registered trademark of AXYS Design Automation, Inc. MaxSim, MaxCore and MaxLib are trademarks of AXYS Design Automation, Inc. All other trademarks are the property of their respective owner.