AXYS Design Enables Multicore C/C++ Simulation of MIPS-based Systems-on-Chip.Business Editors/High-Tech Writers PALO ALTO, Calif.--(BUSINESS WIRE)--April 2, 2001 AXYS Design to Provide Models of Cores Based On the MIPS (Million Instructions Per Second) The execution speed of a computer. For example, .5 MIPS is 500,000 instructions per second; 100 MIPS is a hundred million instructions per second. 32(TM) and MIPS64(TM) Architectures to Complement AXYS Design's Library of Fast and Accurate DSP (1) (Digital Signal Processor) A special-purpose CPU used for digital signal processing applications (see definition #2 below). It provides ultra-fast instruction sequences, such as shift and add, and multiply and add, which are commonly used in math-intensive models AXYS Design Automation, Inc., the leader in fast C/C C/C Center to Center C/C Combustion Chamber C/C Command/Control C/C Crew Chief C/C cabin cruiser (US DoD) C/C chief complaint (medical) C/C Channel-to-Channel C/C Communication and Collaboration ++ based processor modeling and verification solutions for multi-core SoC (system-on-chip) designs, announced today the availability of high-performance, instruction- and cycle-accurate simulation models of cores based upon MIPS Technologies' (Nasdaq:MIPS)(Nasdaq:MIPSB) MIPS32 and MIPS64 architectures. As part of AXYS Design's synchronous multi-core simulation environment MaxSim(TM), these models allow system integrators using MIPS-based embedded processor cores to verify their designs and give embedded software developers a jump-start on development prior to the availability of actual silicon or hardware-based prototypes. Early availability and fast simulation grant software developers a significant amount of extra time to verify and improve the application performance while accelerating time-to-market. "Adding the industry-standard embedded processor cores from MIPS Technologies to our MaxSim library is a further step in our quest to providing our customers with complete cycle-accurate SoC prototyping solutions" said Stefan Tamme, AXYS Design's vice president of marketing and sales. "Multi-processor SoCs always require a proof as early as possible in the design cycle. The use of our prototyping solutions can reduce the time to market by many months." The MaxSim models for the MIPS32 4K(TM) and MIPS64 5K(TM) families of processors can be combined with a variety of DSP and/or other core models available in the MaxSim component library delivering high-speed simulation and enabling synchronous multicore debugging. The MaxSim library includes cores of DSP Group, Infineon, LSI LSI: see integrated circuit. (Large Scale Integration) Between 3,000 and 100,000 transistors on a chip. See SSI, MSI, VLSI and ULSI. Logic, Conexant and others. "MIPS Technologies' licensees are always looking for ways to shorten their chip design phase," said Brian Knowles, vice president of marketing for MIPS Technologies. "We welcome AXYS Design to the MIPS Alliance Program. Their models and simulation environment give development teams using MIPS-based technologies an opportunity to save time and money by substantially reducing the risk of design spins." Editors' Note: Synchronous multi-core simulation and debugging enables the efficient development of real-time software for applications, using multiple embedded processor cores. The system clock is controlled by a central scheduler to ensure that all components of the system advance by the same number of clock cycles, while multiple debugger windows provide full visibility into the internal states of all processors in the system. The cycle budget determined in such a simulation will exactly match the behavior of the actual chip. About AXYS Design Automation, Inc. AXYS Design Automation, Inc. is the leading supplier of fast, accurate, and integrated processor models and related C/C++ based SoC modeling and simulation tools. The LISA The first personal computer to include integrated software and use a graphical interface. Modeled after the Xerox Star and introduced in 1983 by Apple, it was ahead of its time, but never caught on due to its $10,000 price and slow speed. toolset automatically generates cycle-accurate SuperSim(TM) processor models and software development tools from an architectural description in the C-like LISA language. Hierarchical SoC designs can be modeled by combining several SuperSim and other C-models into one cycle-accurate, synchronous multi-core simulation using the MaxSim(TM) environment. The use of AXYS Design's tools and services in the pre-silicon phase substantially shortens the SoC design cycle by enabling early system integration and embedded software development, thus reducing NRE (Non-Recurring Engineering) Refers to the cost of creating a new product, which is paid up front. Contrast with "production cost," which is ongoing and based on the quantity of material produced. cost and the number of silicon spins. AXYS Design's growing SuperSim model portfolio includes processors of Conexant Systems (Nasdaq:CNXT), DSP Group (Nasdaq:DSPG DSPG Defense Special Projects Group ), Infineon Technologies (NYSE NYSE See: New York Stock Exchange : IFX IFX - ["Type Reconstruction with First-Class Polymorphic Values", J. O'Toole et al, SIGPLAN Notices 24(7):207-217 (Jul 1989)]. ) (FSE FSE 1. feline spongiform encephalopathy. 2. focal symmetrical encephalomalacia. :IFX) and LSI Logic (NYSE:LSI). In addition to these SuperSim models, AXYS Design also offers cycle-callable/cycle-accurate models of the ARM (LSE LSE - Language Sensitive Editor :ARM) (Nasdaq:ARMHY) ARM 7 and ARM 9 architectures. For more information, visit the AXYS Design Web site at www.AXYSdesign.com. SuperSim(TM), MaxSim(TM) and MegaModel(TM) are trademarks of AXYS Design Automation, Inc. All other trademarks are the property of their respective owners. |
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