AXYS Announces the High-Performance Cycle-Accurate SuperSim Model for Infineon CARMEL DSP Core.Business Editors & High-Tech Writers IRVINE, Calif.--(BUSINESS WIRE)--June 7, 2000 Seamless-CVE(TM) is the first HW/SW HW/SW Hardware/Software Co-Verification Tool supporting the CARMEL(TM) DSP (1) (Digital Signal Processor) A special-purpose CPU used for digital signal processing applications (see definition #2 below). It provides ultra-fast instruction sequences, such as shift and add, and multiply and add, which are commonly used in math-intensive Core of Infineon Technologies For the raceway, see . Infineon Technologies AG (ISIN: DE0006231004, FWB: IFX, NYSE: IFX) was founded in April 1999 when the semiconductor operations of parent company, Siemens AG, were spun off to form a separate legal entity. AXYS Design Automation Inc. Wednesday announced the development, verification and integration of AXYS' high-performance cycle-accurate SuperSim(TM) model for Infineon's CARMEL DSP Core. The new model is integrated into the Seamless Co-Verification Environment (CVE (Common Vulnerabilities and Exposures) A list of information security exposures and vulnerabilities sponsored by US-CERT and maintained by the MITRE Corporation. ) of Mentor Graphics Mentor Graphics, Inc (NASDAQ: MENT) is a US-based multinational corporation dealing in electronic design automation (EDA) for electrical engineering and electronics, as of 2004, ranked third in the EDA industry it helped create. , which is the first HW/SW co-verification tool to support Infineon's CARMEL DSP. The new cycle-based C model is implemented using AXYS' SuperSim simulation technology and offers a speedup of more than 10,000x compared with the HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. model. Produced in a close cooperation between AXYS and Infineon, it has been verified to achieve 100 percent cycle-by-cycle equivalence with the original HW reference model on Infineon's HW test vectors. Modeled resources include the instruction set architecture with memory and registers, Configurable Long Instruction Word (CLIW CLIW Configurable Long Instruction Word CLIW Course Length in Weeks (TM)) extension, complete pipeline and all pins including the debug To correct a problem in hardware or software. Debugging software means locating the errors in the source code (the program logic). Debugging hardware means finding errors in the circuit design (logical circuits) or in the physical interconnections of the circuits. interface. "When we joined Infineon's DSP Alliance, we committed to providing the highest quality processor models and extensive model integration for Infineon's family of DSP architectures. With the successful development, verification and integration of the SuperSim model for the powerful and complex CARMEL DSP, we have made the first and important step in fulfilling our commitment. As part of our ongoing IP communication efforts, AXYS shall make this unique DSP model available as part of the leading software development and co-verification tools and continue to promote the model-centric view of the system-on-chip development where the different software and hardware design environments are connected over a single high performance processor model," said AXYS' President Vojin Zivojnovic. The CARMEL DSP is a family of 16-bit, fixed-point digital signal processing See DSP. Digital Signal Processing - (DSP) Computer manipulation of analog signals (commonly sound or image) which have been converted to digital form (sampled). (DSP) cores that target advanced communications and consumer applications. Its modular design In the context of systems engineering, modular design — or "modularity in design" — is an approach aiming to subdivide a system into smaller parts (modules) that can be independently created and then used in different systems to drive multiple functionalities. architecture allows for complete system-on-a-chip implementations using advanced electronic design automation methodologies in an integrated development dissipation and code compactness requirements. The patented CLIW architecture sets the core apart by allowing very long instruction word performance at the low cost of traditional DSP architectures. "With AXYS, we can strengthen our customer's design capabilities by providing fast and accurate CARMEL simulation models for system-on-chip design process -- from initial architecture selection and software development -- to HW/SW co-verification and final verification of the silicon," said Shaul Berger, vice president of Infineon Technologies' DSP Cores. "AXYS' advanced simulation technology, combined with their strong verification and integration expertise, enabled us to form an outstanding CARMEL model portfolio." "AXYS' CARMEL DSP processor support package extends the family of highly accurate DSP co-verification models available within Seamless-CVE," said Serge Leef, general manager of Mentor's system-on-chip verification business unit. "Working closely with AXYS and Infineon we are again in the position to be first-to-market with a co-verification platform for a processor of Infineon." The new Seamless-CVE CARMEL model of AXYS will be available over the sales and marketing channels of Mentor Graphics starting in the third quarter of 2000. Other SuperSim CARMEL model integration packages will follow soon. About AXYS AXYS Design Automation is the leading independent supplier of high performance digital signal and embedded processor A CPU chip used in a system other than a general purpose workstation, desktop or laptop computer. Such chips are used by the billions every year in a myriad of products. See embedded system. models, as well as modeling tools to the embedded systems market. AXYS' electronic design automation software and services help the major semiconductor companies and system houses to efficiently specify, design, develop, test, protect and exchange "above-RTL" models of their intellectual property. The SuperSim(TM) model portfolio of AXYS includes processors of Conexant Systems, DSP Group, Infineon Technologies and LSI LSI: see integrated circuit. (Large Scale Integration) Between 3,000 and 100,000 transistors on a chip. See SSI, MSI, VLSI and ULSI. Logic. For more information, visit AXYS Web site at www.axysdesign.com. Note to Editors: SuperSim(TM) is a trademark of AXYS Design Automation; Carmel(TM) is a trademark of Infineon Technologies AG; Seamless-CVE(TM) is a trademark of Mentor Graphics Corp. All other trademarks are the property of their respective companies. |
|
Printer friendly
Cite/link
Email
Feedback
Reader Opinion