AXIOM Design Automation and Averant Form Powerful Alliance.MILPITAS, Calif. -- AXIOM Design Automation and Averant today announced a dynamic new partnership between the two companies that will rapidly advance the adoption and use of formal property checking technology. Averant will integrate AXIOM's popular "Designer" debugging GUI (Graphical User Interface) A graphics-based user interface that incorporates movable windows, icons and a mouse. The ability to resize application windows and change style and size of fonts are the significant advantages of a GUI vs. a character-based interface. with its powerful formal verification
In the context of hardware and software systems, formal verification tool Solidify[TM]. AXIOM's MPSim simulator will also be used in the flow as a platform to demonstrate failed properties to the user. Based on its native simulation, testbench, formal and coverage technology, Designer is rapidly emerging as the next generation debug To correct a problem in hardware or software. Debugging software means locating the errors in the source code (the program logic). Debugging hardware means finding errors in the circuit design (logical circuits) or in the physical interconnections of the circuits. platform. It spans the complete design verification debug spectrum from simulation debug, testbench debug, code and functional coverage debug to constraint failure, formal verification, multi-clock domain verification and design rule checking debug. "We are very excited to be working with AXIOM's Designer product. The combination of our leading edge formal verification technology with Designer's unique debug capabilities will significantly simplify the use and adoption of formal model checking methodology for design and verification engineers," says Ramin Ramin (Gonystylus) is a genus of about 30 species of hardwood trees native to southeast Asia, in Malaysia, Singapore, Indonesia, Brunei, the Philippines, and Papua New Guinea, with the highest species diversity on Borneo. Hojati, president of Averant. Based on its First in Formal[TM] static functional verification Functional verification, in electronic design automation, is the task of verifying that the logic design conforms to specification. In everyday terms, functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a complex task, technology, Averant's Solidify product has become the leading tool in use for formal property checking. "Averant's formal engines, relationship with ARM and patented static code coverage have put them in the lead," said Badru Agarwala, CEO (1) (Chief Executive Officer) The highest individual in command of an organization. Typically the president of the company, the CEO reports to the Chairman of the Board. and founder of Axiom. "The integration with our Designer product will help our customers to be more efficient in their verification flows." About AXIOM Originally founded as @HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. in 1999, AXIOM has been a pioneer in developing functional verification products. The company's mission has always been to accelerate the verification flow and to increase the overall productivity of verification engineers. The introduction of the MPSim multi-CPU simulator provides a quantum leap in verification performance to the industry and enables AXIOM to offer a complete solution to its customers. For more information, see our web site at http://www.axiom-da.com. About Averant Averant Inc., founded in 1997, is a privately held EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. firm pioneering new methodology and technologies for static formal verification. Averant provides Solidify, a robust formal verification engine that provides the basis for property-based design verification, protocol verification, timing constraint verification, and automatic design checks - all without the need for simulators or test vectors. These tools are easily adopted into the design flow, and help improve quality, reduce risk, and speed the design process. For more information, see our web site at http://www.averant.com. |
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