AXIOM Accelerates All Aspects of Functional Verification Including Breakthrough Testbench Parallelization.MILPITAS, Calif. -- AXIOM Design Automation today announced that it has achieved a major milestone in improving functional verification Functional verification, in electronic design automation, is the task of verifying that the logic design conforms to specification. In everyday terms, functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a complex task, performance by enabling SystemVerilog and OpenVera testbench parallelization. The testbench has long been the primary bottleneck A lessening of throughput. It often refers to networks that are overloaded, which is caused by the inability of the hardware and transmission lines to support the traffic. It can also refer to a mismatch inside the computer where slower-speed peripheral buses and devices prevent the CPU in accelerating functional verification. AXIOM's MPSim is the only commercially available simulation product that can leverage multi-CPU hardware to accelerate all aspects of functional verification, including design, testbench, assertions, coverage and debugging (programming) debugging - The process of attempting to determine the cause of the symptoms of malfunctions in a program or other system. These symptoms may be detected during testing or use by real users. . "The industry is rapidly moving towards use of SystemVerilog and adoption of comprehensive testbench methodologies that allow constrained-random stimulus generation, automated checking and functional coverage," said Badru Agarwala, President and CEO (1) (Chief Executive Officer) The highest individual in command of an organization. Typically the president of the company, the CEO reports to the Chairman of the Board. of AXIOM. "With this trend taking hold, an increasing percentage of the simulation time is being consumed by testbench and less in design, even further exasperating the testbench performance bottleneck." MPSim CTB CTB Council Tax Benefit (UK) CTB Coopération Technique Belge (French: Belgian Technical Cooperation) CTB Commonwealth Transportation Board (Virginia Department of Transportation) (Compiled Testbench) can parallelize Par´al`lel`ize v. t. 1. To render parallel. Verb 1. parallelize - place parallel to one another lay, place, put, set, position, pose - put into a certain place or abstract location; "Put your things here"; "Set the testbench by partitioning it across multiple CPUs. This technology utilizes a combination of special features within SystemVerilog, such as multiple program scopes, and simple enhancements built around the OpenVera interface definitions using pragmas. The methodology is ideal for checkers checkers, game for two players, known in England as draughts. It is played on a square board, divided into 64 alternately colored—usually red and black or white and black—square spaces, identical with a chessboard. , monitors and scoreboards and leads to significant acceleration of the overall simulation. To learn more about this technology, users can attend the seminar entitled "Accelerating Function Verification Using Multi-CPU Technology" during the upcoming Design Automation Conference. Availability MPSim and Designer are available immediately. For more information, or to register for the seminar or a demo, please visit the AXIOM website at http://www.axiom-da.com . About AXIOM AXIOM is a pioneer in developing functional verification products. The company's mission is to accelerate the verification flow and to increase the overall productivity of verification engineers. The introduction of the MPSim multi-CPU simulator provides a quantum leap quantum leap n. An abrupt change or step, especially in method, information, or knowledge: "War was going to take a quantum leap; it would never be the same" Garry Wills. in verification performance to the industry and enables AXIOM to offer a complete solution to its customers. AXIOM's integrated verification environment combines the fastest simulator in the industry with advanced testbench automation, assertion based verification, debugging and coverage analysis to ensure that the most complex designs are verified in the least amount of time. AXIOM supports commercially available hardware and industry standard languages including SystemVerilog, Verilog and OpenVera to ensure continuity with your existing verification methodology while offering a clear path to immediate productivity improvement. |
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