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ATI Implements Mentor Graphics Modular TestKompress for Production Test of Advanced 90nm Graphics Processor.


WILSONVILLE, Ore. -- Mentor Graphics Mentor Graphics, Inc (NASDAQ: MENT) is a US-based multinational corporation dealing in electronic design automation (EDA) for electrical engineering and electronics, as of 2004, ranked third in the EDA industry it helped create.  Corporation (Nasdaq:MENT) today announced that ATI Technologies “ATI” redirects here. For other uses, see Ati.
ATI Technologies U.L.C. ATI is a major Canadian designer and supplier of graphics processing units, motherboard chipsets, and video display cards.
 Inc. has implemented the Mentor Graphics TestKompress(R) embedded deterministic test (EDT EDT
abbr.
Eastern Daylight Time


EDT Eastern Daylight Time

EDT n abbr (US) (= Eastern Daylight Time) → hora de verano de Nueva York

EDT 
(TM)) tool. ATI (ATI Technologies Inc., Markham Ontario, http://ati.amd.com) A leading manufacturer of graphics chips and display adapters. Founded in 1985 by K. Y. Ho, Benny Lau and Lee Lau, ATI chips and boards are widely used by OEMs.  used Modular TestKompress, a new block-level implementation of Mentor's EDT methodology that improves compression performance and routing on large, complex devices. Using the new Modular TestKompress, ATI achieved significant compression of test time and test data volume.

"Working closely with Mentor Graphics, we were able to use the TestKompress product to thoroughly test our new chip at no additional test cost," said Michael Do, design for test (DFT DFT - discrete Fourier transform ) architect, ATI Technologies Inc. "Mentor Graphics continues to deliver value-enhancing products."

With device complexity growing and process technologies shrinking, achieving cost-effective high test quality has become increasingly difficult. Test sizes have grown to keep up with design sizes, and nanometer processes have created new challenges, requiring more tests to detect them. The Modular TestKompress tool implements an embedded compression scheme at the block level that dramatically reduces the size of the test sets required for today's complex designs, enabling comprehensive test coverage without sacrificing test throughput. Modular TestKompress provides designers with a block-based flow whereby each block, along with associated compression logic, can be implemented and verified independently. This simplifies the design flow for large block-based designs and reduces the routing area needed to connect the compression hardware.

"ATI is at the forefront of device complexity. Working together, Mentor Graphics adapted the proven TestKompress tool to create a new manufacturing test methodology that solves ATI's test challenges," said Robert Hum, vice president and general manager of the Design Verification and Test division for Mentor Graphics. "This successful implementation of Modular TestKompress highlights Mentor's ability to help its customers achieve higher test quality and lower test cost, even for the most advanced devices and process geometries."

The TestKompress tool fits easily into most scan-based design flows and offers the same at-speed test capabilities as Mentor Graphics FastScan(TM), the industry-leading automatic test pattern generation ATPG (acronym for both Automatic Test Pattern Generation and Automatic Test Pattern Generator) is an electronic design automation method/technology used to find an input (or test) sequence that, when applied to a digital  (ATPG ATPG Automatic Test Pattern Generation
ATPG Automatic Test Program Generator
) tool. The TestKompress tool's patented compression capabilities reduce the amount of test data required for the detection of the speed-related defects that are more prevalent at nanometer process technologies.

About Mentor Graphics Design-for-Test Tools

Mentor Graphics provides the industry's broadest portfolio of DFT solutions for today's System-on-Chip and deep submicron designs, including integrated solutions for scan, ATPG, EDT, advanced memory test, boundary scan See scan technology.

boundary scan - The use of scan registers to capture state from device input and output pins. IEEE Standard 1149.1-1990 describes the international standard implementation (sometimes called JTAG after the Joint Test Action Group which began the
, logic built-in self-test A built-in self-test (BIST) mechanism within an integrated circuit (IC) is a function which verifies all or a portion of the internal functionality of the IC. For example, a BIST mechanism is provided in advanced fieldbus systems to verify functionality.  and a variety of DFT-related flows. For more information, visit www.mentor.com/products/dft.

About Mentor Graphics

Mentor Graphics Corporation (Nasdaq:MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of over $700 million and employs approximately 4,000 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon Wilsonville is a city in Clackamas County, Oregon, United States. The population was 13,991 at the 2000 census, and as of 2005 was estimated to be 16,510.[1] Geography
Wilsonville is located at  (45.306805, -122.
 97070-7777. World Wide Web site: http://www.mentor.com/.

Mentor Graphics and TestKompress are registered trademarks and FastScan is a trademark of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.
COPYRIGHT 2006 Business Wire
No portion of this article can be reproduced without the express written permission from the copyright holder.
Copyright 2006, Gale Group. All rights reserved. Gale Group is a Thomson Corporation Company.

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Publication:Business Wire
Article Type:Company overview
Geographic Code:1CANA
Date:Jun 20, 2006
Words:521
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