ASSET's innovative design-for-test tool, DFT Analyzer(TM), named finalist for IEC DesignVision Award.RICHARDSON, Texas -- Recognizing that ASSET[R] InterTech's design-for-test tool, DFT DFT - discrete Fourier transform Analyzer, offers innovative assistance to PCB PCB: see polychlorinated biphenyl. PCB in full polychlorinated biphenyl Any of a class of highly stable organic compounds prepared by the reaction of chlorine with biphenyl, a two-ring compound. design and test engineers, the International Engineering Consortium (IEC (International Electrotechnical Commission, Geneva, Switzerland, www.iec.ch) An organization that sets international electrical and electronics standards founded in 1906. It is made up of national committees from over 60 countries. IEC - International Electrotechnical Commission ) has made DFT Analyzer a finalist for a 2007 DesignVision Award. ASSET (www.asset-intertech.com) is an international leader in boundary-scan (JTAG/IEEE 1149.1) technology for design, test and programming. "Our DesignVision Awards honor those catalyzing positive change in high-technology, business, and academia, completely in line with the IEC's mission," said IEC President John Janowiak. "We are delighted to recognize our DesignVision Finalists and share the best design advancements and innovations with the entire industry." ASSET's DFT Analyzer was one of three finalists in the printed circuit board (PCB) design tool category. Winners will be announced at the upcoming DesignCon exhibition and conference, Jan. 29 through Feb. 1 in the Santa Clara Convention Center. ASSET will be demonstrating DFT Analyzer in its booth at DesignCon, Booth No. 918. Entries in the DesignVision program were judged on the basis of their innovation, uniqueness, market impact, customer benefits and value to society. "To capitalize effectively on the many benefits of boundary scan technology, JTAG (Joint Test Action Group) An IEEE standard for boundary scan technology. See scan technology. JTAG - Joint Test Action Group should be a consideration during the design of circuit boards and chips," said Alan Sguigna, vice president of sales and marketing for ASSET. "This is becoming even more critical these days because additional technologies, like IEEE (Institute of Electrical and Electronics Engineers, New York, www.ieee.org) A membership organization that includes engineers, scientists and students in electronics and allied fields. 1149.6 for testing high-speed AC-coupled buses and Intel[R] IBIST (Interconnect Built In Self Test), depend upon the JTAG infrastructure to perform their functions. The better boundary scan is designed into boards and chips, the greater the benefit that manufacturers derive from it, beginning with prototype debug To correct a problem in hardware or software. Debugging software means locating the errors in the source code (the program logic). Debugging hardware means finding errors in the circuit design (logical circuits) or in the physical interconnections of the circuits. in design and following a product through to manufacturing and support." About ASSET InterTech ASSET InterTech, Inc. develops, markets, sells, and supports boundary-scan design tools, test technology and in-system programming (ISP (1) See in-system programmable. (2) (Internet Service Provider) An organization that provides access to the Internet. Connection to the user is provided via dial-up, ISDN, cable, DSL and T1/T3 lines. ) products worldwide. ASSET's ScanWorks[R] test system and the DFT Analyzer[TM] circuit board design tool are affordable, easy-to-use and powerful. For product information, call toll free 888-694-6250, send faxes to 972-437-2826, direct e-mail to sales@asset-intertech.com or visit the company's Web site at www.asset-intertech.com |
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