ASSET's New Design-for-Test Lab Validates JTAG Capabilities in Chip and Board Designs.Free Testability Analysis Improves Yields on Prototype Designs RICHARDSON, Texas Richardson is a suburb in Dallas County and Collin County, Texas. As of the 2000 census, the city had a total population of 91,803, while according to a 2006 estimate, the population had grown to 99,200. -- ASSET[R] InterTech, Inc., (www.asset-intertech.com) an international leader in boundary-scan (JTAG/IEEE 1149.1) test and in-system programming In-System Programming (abbreviated ISP) is the ability of some programmable logic devices, microcontrollers, and other programmable electronic chips to be programmed while installed in a complete system, rather than requiring the chip to be programmed prior to installing it into (ISP (1) See in-system programmable. (2) (Internet Service Provider) An organization that provides access to the Internet. Connection to the user is provided via dial-up, ISDN, cable, DSL and T1/T3 lines. ), has opened the industry's first Design-for-Test (DFT DFT - discrete Fourier transform ) Lab for validating the JTAG (Joint Test Action Group) An IEEE standard for boundary scan technology. See scan technology. JTAG - Joint Test Action Group infrastructure in chip and printed circuit board designs. The lab will offer a free analysis of pre-prototype designs and advice to ensure that the JTAG infrastructure can be effectively deployed in its traditional structural test applications as well as in advanced applications that take advantage of the JTAG infrastructure. "Today there are several test and programming methodologies which depend upon an effective boundary-scan infrastructure. Without a properly designed JTAG infrastructure, these advanced methodologies can't perform their functions," said Arden Bjerkeli, ASSET's director of support. "Quite often, design or verification engineers are not familiar with some of the finer points of JTAG design-for-test. The DFT Lab can strengthen the JTAG infrastructure in chip and circuit board designs before samples or prototypes are ever produced. That means that development and production schedules can be maintained and expensive re-designs following prototype production will be avoided." ASSET's first DFT Lab is located in Silicon Valley at 2033 Gateway Place, Suite 600, San Jose San Jose, city, United States San Jose (sănəzā`, săn hōzā`), city (1990 pop. 782,248), seat of Santa Clara co., W central Calif.; founded 1777, inc. 1850. , CA 95110. The services of the lab are available to first-time users of boundary scan See scan technology. boundary scan - The use of scan registers to capture state from device input and output pins. IEEE Standard 1149.1-1990 describes the international standard implementation (sometimes called JTAG after the Joint Test Action Group which began the . Scott Creekpaum has been named manager of the lab. The free analysis and design recommendations will be performed with ASSET's DFT Analyzer[TM], the industry's only tool that automatically verifies the JTAG testability of board designs. The accuracy of a chip design's Boundary-scan Description Language (BSDL (Boundary Scan Description Language) An IEEE language used to describe structures for boundary scan testing. See scan technology. ) file will be verified with the BSDL Validation Service, a collaborative effort of ASSET and Agilent Technologies, Inc. In addition, other tools can be applied to board and chip designs to validate their JTAG capabilities. About ASSET InterTech ASSET InterTech, Inc. develops, markets, sells, and supports boundary-scan design tools, test technology and in-system programming (ISP) products worldwide. ASSET's ScanWorks[R] test system and the DFT Analyzer[TM] circuit board design tool are affordable, easy-to-use and powerful. For product information, call toll free 888-694-6250, send faxes to 972-437-2826, direct e-mail to sales@asset-intertech.com or visit the company's Web site at www.asset-intertech.com. |
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