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ARM Announces 2GHz Capable Cortex-A9 Dual Core Processor Implementation.


ARM Cortex Processor Technology and Physical IP Developed in Unison to Deliver High Performance and Low-Power Processing for Consumer and Enterprise Markets

CAMBRIDGE, England -- ARM (LSE LSE - Language Sensitive Editor :ARM) (Nasdaq:ARMH ARMH Asociación para la Recuperación de la Memoria Histórica (Spanish)
ARMH Atlanta Ronald McDonald House
ARMH Academy of Religion and Mental Health
) announced today the development of two Cortex[TM]-A9 MPCore[TM] hard macro The design of a logic function on a chip that specifies how the required logic elements are interconnected and specifies the physical pathways and wiring patterns between the components. Also called a "macro cell." Contrast with soft macro.  implementations for the TSMC TSMC Taiwan Semiconductor Manufacturing Company, Ltd
TSMC Taiwan Semiconductor Manufacturing Corporation
TSMC Traffic Systems Management Center
TSMC Toll Station Management Controller
TSMC Transportation Supply Maintenance Command
TSMC Technical Services Manager Code
 40nm-G process, enabling silicon manufacturers to have a rapid and low-risk route to silicon for high-performance, low-power Cortex-A9 processor-based devices. The speed-optimized hard macro implementation will enable devices to operate at frequencies greater than 2GHz.

The dual core hard macro implementations are the result of ARM's significant investment in advanced physical IP development in unison with processor and fabric IP technology, and leading-edge implementation flows from the EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board.  industry. Advanced physical IP techniques have enabled critical circuits within the design to be replaced with highly tuned logic cells and memories, increasing performance while lowering overall power consumption.

Speed Optimized

The Cortex-A9 speed-optimized hard macro implementation will provide system designers with an industry standard ARM[R] processor incorporating aggressive low-power techniques to further extend ARM's performance leadership into high-margin consumer and enterprise devices within the power envelope necessary for compact, high-density and thermally constrained environments. This hard macro implementation operates in excess of 2GHz when selected from typical silicon and represents an ideal solution for high-margin performance-oriented applications.

Power Optimized

In many thermally constrained applications such as set-top boxes, DTVs, printers and other feature-rich consumer and high-density enterprise applications, energy efficiency is of paramount importance. The Cortex-A9 power-optimized hard macro implementation delivers its peak performance of 4000 DMIPS DMIPS Dhrystone MIPS (Million Instructions Per Second)  while consuming less than 250mW per CPU CPU
 in full central processing unit

Principal component of a digital computer, composed of a control unit, an instruction-decoding unit, and an arithmetic-logic unit.
 when selected from typical silicon.

The hard macro implementations include ARM AMBA AMBA Area Metropolitana de Buenos Aires (Spanish)
AMBA Advanced Microcontroller Bus Architecture
AMBA American Mold Builders Association
AMBA American Mustang and Burro Association
AMBA Association of Master of Business Administration
[R]-compliant high performance system components to maximize data traffic speed and minimize power consumption and silicon area. Each Cortex-A9 hard macro implementation also includes the CoreSight[TM] Program Trace Macrocell (PTM PTM Post-Translational Modifications
PTM Porsche Traction Management
PTM Point-To-Multipoint
PTM Please Tell Me
PTM Packet Transfer Mode
PTM Pulse-Time Modulation
PTM Portugal The Man (band)
PTM Predictive Technology Model
) which provides full visibility into the processor's instruction flow, enabling the software community to develop code for optimal performance.

"The Cortex-A9 MPCore processor has already been widely accepted as the processor of choice for high-performance embedded applications across a broad spectrum of demanding consumer and enterprise devices," said Eric Schorn, VP marketing, Processor Division, ARM. "ARM's parallel development of advanced, optimized physical IP components demonstrates a new level of collaborative differentiation while enabling our Partners to expand their penetration into high margin domains traditionally occupied by proprietary architectures."

"ARM's long-standing investment in low-power leadership and ability to develop such high-performance devices enables licensees to lower the cost and risk of entering the high-margin markets currently addressed with competing proprietary solutions," said Will Strauss, principal analyst at Forward Concepts. "With single-thread performance capable of supporting very intensive workloads, the unprecedented level of power efficiency will enable licensees to introduce compelling new products."

"ARM and TSMC have enjoyed a long standing relationship of collaboration to ensure the development and delivery of best-in-class products optimized for our manufacturing process," said ST Juang, senior director, Design Infrastructure Marketing Division, TSMC. "This provides OEMs developing feature-rich consumer and enterprise devices access to TSMC's manufacturing excellence and the power of ARM processor IP."

Both ARM dual core Cortex-A9 hard macros will share a common seven-power domain, dual-NEON[TM] technology configuration supporting SMP (Symmetric MultiProcessing) A multiprocessing architecture in which multiple CPUs, residing in one cabinet, share the same memory. SMP systems provide scalability. As business increases, additional CPUs can be added to absorb the increased transaction volume.  (symmetrical multiprocessing) operating systems Operating systems can be categorized by technology, ownership, licensing, working state, usage, and by many other characteristics. In practice, many of these groupings may overlap.  with up to 8MB of Level2 cache memory and will be delivered with all scripts, vectors and libraries required to integrate the macro directly within any SoC device.

To enable the development of high-efficiency, low risk SoCs using other Cortex-A9 processor configurations, ARM also provides the silicon-proven SoC-level ARM Physical IP platform used to build these hard macros, and a range of AMBA-compliant system development components and tools.

In addition, the ARM Active Assist consulting service Noun 1. consulting service - service provided by a professional advisor (e.g., a lawyer or doctor or CPA etc.)
service - work done by one person or group that benefits another; "budget separately for goods and services"
, developed in conjunction with the hard macros, enables ARM Partners to efficiently integrate the hardened macro into their SoC design to realize maximum system performance with lowest risk and fastest time-to-market.

Availability

The Cortex-A9 hard macros and the corresponding optimized physical IP used to develop the speed-optimized and power-optimized implementations are available for license today with delivery in the fourth quarter of 2009. ARM's 40G physical IP platform is also available today at designstart.arm.com.

About ARM

ARM designs the technology that lies at the heart of advanced digital products, from wireless, networking and consumer entertainment solutions to imaging, automotive, security and storage devices. ARM's comprehensive product offering includes 32-bit RISC RISC
 in full Reduced Instruction Set Computing

Computer architecture that uses a limited number of instructions. RISC became popular in microprocessors in the 1980s.
 microprocessors, graphics processors, video engines, enabling software, cell libraries, embedded memories, high-speed connectivity products, peripherals and development tools. Combined with comprehensive design services, training, support and maintenance, and the company's broad Partner community, they provide a total system solution that offers a fast, reliable path to market for leading electronics companies. More information on ARM is available at http://www.arm.com.

ARM is a registered trademark of ARM Limited. Cortex, MPCore, AMBA and NEON are trademarks of ARM Limited. All other brands or product names are the property of their respective holders. "ARM" is used to represent ARM Holdings plc; its operating company operating company

A business that engages in transactions with outsiders.
 ARM Limited; and the regional subsidiaries: ARM, Inc.; ARM KK; ARM Korea Ltd.; ARM Taiwan Limited; ARM France SAS (1) (SAS Institute Inc., Cary, NC, www.sas.com) A software company that specializes in data warehousing and decision support software based on the SAS System. Founded in 1976, SAS is one of the world's largest privately held software companies. See SAS System. ; ARM Consulting (Shanghai) Co. Ltd.; ARM Belgium N.V.; AXYS Design Automation Inc.; ARM Germany GmbH; ARM Embedded Technologies Pvt. Ltd.; and ARM Norway ARM Norway (before June 2006: Falanx) is a Norwegian company located in Trondheim, owned by ARM Holdings. ARM Norway develops graphics accelerators for OpenGL three-dimensional rendering as well as for MPEG4 video, with emphasis on low electric power consumption, suitable , AS; and ARM Sweden AB.
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Publication:Business Wire
Date:Sep 16, 2009
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