ARM AND SYNOPSYS REDUCE TIME-TO-MARKET FOR ARM CORE-BASED DESIGNS.

ARM [(LSE: ARM); (Nasdaq: ARMHY)], an industry provider of 16/32-bit embedded RISC microprocessor solutions, and Synopsys, Inc. (Nasdaq: SNPS), the technology leader for complex IC designs, has announced a jointly-developed reference design flow that streamlines the methodology used by ARM Partners to port ARM microprocessor cores to their process technologies. The register transfer level (RTL) to GDSII reference design flow shortens time-to-market for ARM core-based designs. The fully integrated reference design flow is initially available for the ARM946E-S synthesizable microprocessor core and provides for the customization, re-implementation, re-verification and characterization of the core by leveraging Synopsys' advanced EDA technology.

"Providing a superior reference design flow is strategic to our business. When we enable Partners to do their own porting starting from synthesizable ARM cores, we must provide proven methods for retaining compliance with our architecture in their porting process," said Simon Segars, vice president, Engineering, ARM. "This new flow not only ensures architectural integrity, but it has significantly reduced implementation time on early core hardenings. This gives our Partners a significant market advantage. The reference design flow will become the foundation methodology for our soft IP core solution."

"The new reference design flow allows us to take the ARM946E-S core in RTL, re-implement it very quickly to our process and get a deterministically accurate, architecturally-compliant hardened core," said Luciano Raimondi, application specific DSP/ARM cores design manager of STMicroelectronics' TPA Groups. "We successfully evaluated the timing model extraction portion of the flow this summer and we are now introducing this flow in our sign-off procedure for use in future ARM projects."

The flow provides a predictable route to silicon using both logical and physical synthesis technologies and allows rapid technology and application- specific implementations of ARM cores optimized for performance, area and power. All necessary design views of the physical implementation are created to enable the rapid integration of the ARM core into a system-on-chip (SoC) design. The initial release of the flow includes Synopsys' Physical Compiler, Chip Architect, Design Compiler, DC Ultra, DesignWare, Power Compiler, Formality, DFT Compiler, TetraMAX, PrimeTime and VCS. The reference design flow is modular and based on standard interfaces allowing for the integration of complementary tools.

The reference flow is the first result of an ongoing collaboration between Synopsys and ARM. "ARM and Synopsys developed a reference design flow that enables ARM Partners to easily characterize and create all necessary design views of their own implementation," said Rich Goldman, vice president of Strategic Market Development for Synopsys. "This approach not only serves ARM's direct Partners, but end designers of ARM Powered products can more rapidly integrate an ARM core into their products using the new reference design flow."

The ARM-Synopsys RTL to GDSII reference design flow will be available in November 2001 to ARM Partners as an Implementation Guide for the ARM946E-S microprocessor core, along with supporting scripts.