ARC and Cadence Announce Optimized Integration of Encounter(R) Digital IC Platform with ARChitect Processor Configurator.

ELSTREE, England & SAN JOSE, Calif. -- The Companies Deepen Their Collaboration Through the OpenChoice IP Program to Deliver Enhanced Productivity to Mutual Customers

In sub-one hundred nanometer process geometries, capacitance, inductance, resistance and cross-talk all conspire to thwart a design team's efforts to produce right-first-time silicon that meets critical timing and power budgets. To address this industry-wide challenge, Cadence Design Systems, Inc. (NASDAQ:CDNS) and ARC International (LSE:ARK) today announced the companies have integrated optimized support of the Cadence(R) Encounter(R) digital integrated circuit (IC) design platform into ARC's patented ARChitect(TM) processor configuration tool. Using ARChitect, ARC licensees now can produce RTL, synthesis and floorplanning scripts that are tuned to the Encounter reference methodology. This will help the system-on-chip (SoC) designer better anticipate the behavior of electrical signals and ensure the design is fully verified before going to silicon.

The companies also announced that ARC has joined Cadence's OpenChoice IP Program and become one of Cadence's featured intellectual property (IP) partners.

"By collaborating with ARC International, our mutual customers can get to market quickly with highly optimized silicon through the use of best-in-class configurable and EDA technologies," said Jan Willis, senior vice president of Industry Alliances at Cadence. "Through the OpenChoice IP program, Cadence and ARC will continue to work together to ensure SoC designers using our products continue to benefit from the fruits of our deepening partnership."

The Cadence Encounter Digital IC Platform provides an integrated RTL-to-GDSII design environment -- from RTL synthesis and test design through physical prototyping and partitioning to final timing and manufacturing closure. Encounter offers highest quality of silicon (timing, area, and power with wires), accurate verification, SI-aware routing, and the latest yield and low power design capabilities that are critical for the advanced designs of ARC's customers.

"Cadence Encounter design platform provides a proven path to silicon for all of the ARC 600 and ARC 700 configurable core families and multimedia subsystems by characterizing and accommodating all the circuit effects that proliferate in the interconnect layers of nanometer processes," said Peter Hutton, senior vice president of engineering at ARC. "Thus our customers can let the tool handle the noncreative part of the design flow, freeing them to be creative using the ARChitect processor configuration tool to add or remove components in ARC cores to achieve additional functionality -- enabling higher margins and more differentiation from competitors. We look forward to continuing our close collaboration with Cadence through the OpenChoice IP program."

ARChitect Processor Configuration Tool

ARChitect Processor Configurator enables SoC designers to rapidly create customized ARC processor core designs optimized for specific applications, without increasing project complexity or risk. Using the ARChitect tool's drag-and-drop GUI, designers can include features they need and remove those not needed for their application. Configuration options include features around the core such as type and size of caches, interrupts, DSP subsystems, timers and debug components, as well as features within the core such as type and size of core registers, address bus widths, and instruction set options. Performance and die size tradeoffs are quickly accomplished, resulting in an optimized solution. The resulting core invariably will be smaller and lower power than "fixed architecture" cores.

Encounter Reference Methodology

The Cadence Encounter(R) Reference Methodology integrated into ARChitect allows designers to quickly create a detailed, full-chip, silicon virtual prototype including characterized routed wires. Integral to the platform is a flexible graphical user interface, a customized flow, the ARC 600 or ARC 700 configurable core families reference designs, and a base technology/library infrastructure. The methodology provides completely validated synthesis and floorplanning scripts to enable users to implement the latest technology quickly, with minimal ramp-up time.

Cadence OpenChoice IP Program

The Cadence OpenChoice IP program enables interoperability and facilitates open collaboration with leading IP providers to build, validate, and deliver accurate models for Cadence design and verification solutions. The program aims to ensure IP quality, integration, and provides engineers access to a broad IP offering through a complete IP catalog. This optimizes the electronics design chain and accelerates customer time to market.

Availability

The ARChitect(TM) processor configuration tool with integrated optimized support of the Cadence(R) Encounter(R) digital integrated circuit (IC) design platform is available immediately.

About Cadence

Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, printed circuit boards and systems used in consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2005 revenues of approximately $1.3 billion, and has approximately 5,000 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

About ARC International plc

ARC International is the world leader in low-power, high-performance 32-bit configurable CPU/DSP processor cores, subsystems, real-time operating systems and development tools for embedded system design. ARC's patented configurable CPU technology assists customers in the development of next generation digital media, consumer and communications devices, resulting in lower cost, higher performance SoC products.

ARC International maintains a worldwide presence with corporate offices in San Jose, California, USA and Elstree, UK. The company has research and development offices located in England and the United States. For more information please visit the ARC website at: www.ARC.com. ARC International is listed on the London Stock Exchange as ARC International plc (LSE:ARK).

ARC, the ARC logo and ARC-Based are trademarks or registered trademarks of ARC International. Cadence, Cadence logo and Encounter are registered trademarks of Cadence Design Systems in the United States and other countries. All other brands or product names contained herein are the property of their respective owners. This press release may contain certain "forward-looking statements" that involve risks and uncertainties. For factors that could cause actual results to differ, visit the company's Website as well as the listing particulars filed with the United Kingdom Listing Authority and the Registrar of Companies in England and Wales.