ARC Cores Selects Synopsys High-Level Design Tools for SoC Evaluation Platform.Business Editors/High Tech Writers SAN JOSE, Calif.--(BUSINESS WIRE) Oct. 23, 2000 - ARC Cores has signed an agreement with Synopsys, Inc. (NASDAQ NASDAQ in full National Association of Securities Dealers Automated Quotations U.S. market for over-the-counter securities. Established in 1971 by the National Association of Securities Dealers (NASD), NASDAQ is an automated quotation system that reports on :SNPS SNPS Space Nuclear Power System ) to provide a suite of high-level design tools for ARC's processor evaluation platform. The platform, which is designed to prototype and benchmark devices incorporating the configurable ARC processor, will integrate Synopsys' design software, creating a comprehensive system-on-chip development tool chain. The ARC evaluation platform combines ARC's ARChitect tool, key Synopsys products and a Sun Microsystems Ultra(TM) 5 workstation that has been secured to prevent unauthorized use of intellectual property during evaluation. Also included in the platform is ARC's MetaWare software development tool chain with a C/C C/C Center to Center C/C Combustion Chamber C/C Command/Control C/C Crew Chief C/C cabin cruiser (US DoD) C/C chief complaint (medical) C/C Channel-to-Channel C/C Communication and Collaboration ++ compiler and debugger, in addition to a VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. compiler/simulator. According to Andy Elms, director of worldwide customer support at ARC Cores, "Inclusion of the Synopsys tools allows users to fully benchmark their proposed system prior to purchasing the ARC microprocessor IP." He continues, "Designers require both comprehensive design environments and tools to ensure that their design is optimized for the appropriate system performance metrics. Using Synopsys tools as an integral part of our evaluation platform, designers have access to best-in-class EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. tools to fully prove their concepts -- whether sensitive to power consumption, area or speed -- before making any firm commitment." The ARC evaluation platform incorporates the ARChitect tool for configuring the ARC processor and generating VHDL or Verilog RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; . Output from the ARChitect tool is then passed directly to a comprehensive suite of Synopsys high-level design tools. The suite includes: DC Expert Plus (TM) leading-edge ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. synthesis with design-for-test capabilities, DesignWare(R) IP Library, FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market. Compiler II(TM) advanced synthesis for multimillion-gate FPGA designs, and Power Compiler(TM) for push-button (electronics) push-button - A roughly fingertip-sized plastic cover attached to a spring-loaded, normally-open switch, which, when pressed, closes the switch. Typical examples are the keys on a computer or calculator keyboard and mouse buttons. power reduction and RTL power estimation. "By including Synopsys software in the evaluation platform ARC's customers can evaluate the processor in their preferred environment," said Laura Horsey hors·y also hors·ey adj. hors·i·er, hors·i·est 1. Of, relating to, or resembling horses or a horse. 2. Devoted to horses and horsemanship: the horsy set. 3. , manager, IP partnerships at Synopsys. "The breadth and comprehensiveness of the Synopsys portfolio is the perfect match for ARC's configurable processor, allowing designers maximum flexibility to achieve their specific system design goals." About ARC Cores ARC Cores (a subsidiary of ARC International plc) is a leading designer and developer of customizable, high-performance microprocessor cores and related intellectual property solutions for integrating microprocessors with embedded systems applications. The ARC processor is an application specific processor or ASP, which can be customized for use in a wide variety of increasingly sophisticated products, including telecommunications, voice and data networking, and consumer electronics products. ARC's technology enables designers to rapidly develop prototype designs for validation of design concepts, to reduce the cycle time between design, development and physical prototype to the launch of a product. With headquarters in Elstree, England, ARC International plc and its group companies employ over 200 people in research and development, sales, and marketing offices across North America and Europe. MetaWare, Precise Software Technologies and VAutomation are wholly owned subsidiaries Wholly Owned Subsidiary A subsidiary whose parent company owns 100% of its common stock. Notes: In other words, the parent company owns the company outright and there are no minority owners. of ARC International plc, providing software development tools, hardware and software intellectual property and real time operating systems offering a single source solution when required for system on a chip development. The company's website is located at: http://www.arccores.com or phone: +44 (0) 20 8236 2800 (UK) or +1 408 360 2120 (USA). Note to Editors: ARC Cores is a trademark of ARC International (UK) Limited. All other brands or product names are the property of their respective holders. |
|
||||||||||||||||

Printer friendly
Cite/link
Email
Feedback
Reader Opinion