AMD selects Atrenta's SpyGlass to predict downstream design issues early in the design cycle.

Atrenta Inc. has announced that AMD's Personal Connectivity Solutions Group (PCS) has selected Atrenta's SpyGlass Predictive Analyzer and SpyGlass Design For Testability (DFT) to predict critical testability and Register Transfer Language (RTL) handover issues right up front at RTL, before lengthy synthesis and simulation runs, thereby saving months of re-coding, re-synthesis and re-verification cycles. AMD chose SpyGlass because of its unique predictive analysis technique, which enables it to perform detailed structural analysis at RTL and to identify complex issues such as clock domain crossings, synchronization and testability issues early in the design cycle.

"SpyGlass allows us to immediately and efficiently check a wide range of problems before moving into subsequent design phases, where corrections are time consuming and costly," said Peggy Nissen, AMD's computer aided design manager for PCS. "With SpyGlass, the DFT team now has an automated, less intrusive way to communicate DFT requirements to the design teams and to apply DFT checks early to find bugs that had previously caused schedule delays. SpyGlass offers an automated approach to check the downstream design requirements at RTL creation."

"By identifying complex design issues such as clock domain crossings and testability problems early at RTL, SpyGlass reduces late gate level to RTL iterations and helps AMD minimize development costs and achieve more predictable schedules," said Ghulam Nurie, Senior Vice President of Marketing and Business Development at Atrenta.

SpyGlass employs a unique predictive analysis technique that looks at the structure of the design and finds downstream problems that are not detectable by other methods including other rule checkers, simulators and formal verifiers. Atrenta has developed an advanced technology that uses fast synthesis to create a flat gate-level representation so true structural analysis can be performed during the RTL design phase. This enables SpyGlass to detect, at the RT level, very complex design problems such as clock domain crossings, synchronization, tri-state bus decoding, combinational loops, logic cone depth, and complex testability issues. Design errors are reported back to the original RTL and a graphical debugging environment helps in quick problem isolation.

Users can efficiently utilize Atrenta provided pre-packaged rules, which represent the best design practices in the industry as well as create new proprietary and customized checks that address their company specific guidelines in both VHDL and Verilog.

Atrenta offers a new approach in accelerating the design of complex SoCs, ASICs, and FPGAs through predictive analysis. Its award-winning SpyGlass software is the first tool that performs detailed structural analysis on register-transfer-level Verilog and VHDL code in order to check for complex problems, which include coding styles, RTL-handoff, design re-use, clock/reset requirements, DFT and much more. Its breakthrough and innovative "look-ahead" capability incorporates a fast-synthesis engine, logic evaluator, and testability technologies. Atrenta has over fifty customers, including Agere, Agilent, Apple, ARM, Canon, Compaq, Fujitsu, Hitachi, Motorola, National Semiconductor, Nortel, Olympus, and Toshiba, who are using SpyGlass to achieve shorter overall design cycles, increased design productivity and lower costs. SpyGlass was selected by EDN magazine as one of the Top 100 products for 2002 and the tool received the "LSI Design of The Year 2002" award by Japan's Semiconductor Industry News. Additionally, Atrenta was chosen by Venture Reporter as one of the top 100 venture-backed companies for 2002.