AIST Develops Upright-type Double-gate MOS Transistor Capable of Ultra-large Scale Integration.Tokyo, Japan, Jan 17, 2006 - (JCN JCN Japan Corporate News JCN Journal of Cognitive Neuroscience JCN Journal of Cardiovascular Nursing JCN Journal of Christian Nursing JCN Job Control Number JCN Journal of Child Neurology JCN joint communications network (US DoD) ) - The National Institute for Advanced Industrial Science and Technology (AIST AIST Advanced Industrial Science and Technology (Japan) AIST National Institute of Advanced Industrial Science and Technology (Japan) AIST Association for Iron & Steel Technology ) and Tohoku University This article is Tohoku University in Japan. The same name university in China, 東北大学, is Northeastern University (Shenyang, China). Tohoku University ( announced the manufacture of a high-performance upright-type double gate MOS (1) (Metal Oxide Semiconductor) See MOSFET. (2) (Mean Opinion Score) The quality of a digitized voice line. It is a subjective measurement that is derived entirely by people listening to the calls and scoring the results from transistor capable of ultra-large scale integration using neutral beams which cannot damage silicon substrates. As competition in developing and miniaturizing new materials increases, silicone plays a particularly important role in driving the industry, and research into high performance silicone is crucial for remaining competitive. Successful development requires the miniaturization min·i·a·tur·ize tr.v. min·i·a·tur·ized, min·i·a·tur·iz·ing, min·i·a·tur·iz·es To plan or make on a greatly reduced scale. min of high-performance integrated circuits. With conventional techniques designed for the fabrication fabrication (fab´rikā´sh  n),n the construction or making of a restoration. of 2D-spreading devices, however, the heat caused by leakage-current from miniaturized circuit elements is so great that it is extremely difficult to develop ultra-large scale integration circuits for the 32-nm technology generation. Against this technical barrier, AIST has been developing a 3D, upright-type double-gate MOS transistor, which not only can suppress the leakage-current that causes heat generation but can be highly integrated. AIST has combined this technique with a nearly damage-free etching technique using neutral beams, developed by Prof. Seiji Samukawa of Tohoku University, and created an upright-type double-gate MOS transistor which enables ultra-large scale integration. This transistor has an etched surface flatness of less than 1 nm in irregularity A defect, failure, or mistake in a legal proceeding or lawsuit; a departure from a prescribed rule or regulation. An irregularity is not an unlawful act, however, in certain instances, it is sufficiently serious to render a lawsuit invalid. , and has high electron mobility. Moreover, the performance of the transistor is found to be 30% better than that of the transistors fabricated by conventional processing techniques, suggesting that the AIST technique may be promising for ultra-fine circuit fabrication in the 32-nm technology generation. This work was presented on December 7 at the 2005 International Electron Device Meeting, which was held at Washington, DC from December 5 to 7. Copyright [c] 2006 Japan Corporate News Network. All rights reserved. |
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