ADVISORY/Tutorial On SUPERLOG Design Language to be Taught During HDLCon 2001 February 28.

News/Assignment Editors

ADVISORY...for Wed. (Feb. 28)

--(BUSINESS WIRE)

SUPERLOG: A Practical Approach to System Verification and Hardware Design WHAT:
Tutorial on using SUPERLOG(TM)in advanced methodologies for large-scale design
and verification projects. SUPERLOG is a superset of the Verilog Hardware
Description Language (HDL) and the new Verilog 2000 HDL proposal. It includes
programming constructs based on the C Software Programming Language and
additional capabilities for system modeling and advanced verification
environments. The language evolves current Verilog modeling techniques to
accelerate verification environments and streamline abstract design through
synthesis. Previously undisclosed SUPERLOG capabilities will be highlighted,
together with practical examples of its use. WHEN: Wednesday, February 28, from
1:00 p.m. to 4:30 p.m. WHERE: Santa Clara Marriott Hotel, Santa Clara, Calif.,
as part of the HDLCon 2001, sponsored by Accellera WHY: The SUPERLOG design
language from Co-Design Automation Inc. allows Verilog HDL-based models to be
evolved using abstract modeling constructs and verification capabilities,
enabling significant productivity improvements with minimal investment. WHO:
The tutorial instructors will be Peter Flake, chief technology officer, and
David Rich, director of application engineering at Co-Design. Design and
verification engineers interested in learning how to improve productivity
should attend. FEES: $200 per person for conference attendees registered for at
least one day of the conference. Fees include course materials. RSVP: MP
Associates Inc., HDLCon Organizers For tutorial availability: [phone]
For conference information: http://www.hdlcon.org

SUPERLOG is a trademark of Co-Design Automation, Inc. Co-Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services.