ADVISORY/Tera Systems' CEO Tommy Eng to Participate in Panel on RTL Signoff at DAC 2002 in New Orleans on June 12.Business Editors/High-Tech Writers Design Automation Conference 2002 ADVISORY ... for Wednesday Wednesday: see week. (June June: see month. 12) --(BUSINESS WIRE) WHAT: Panel titled, "Whither (or Wither?) ASIC Handoff," chaired by Michael Santarini ABSTRACT: The traditional ASIC netlist handoff is changing -- but to what? Is RTL handoff finally a reality? Or, will a placement-based handoff model emerge? Are differences among underlying tool technologies and methodologies only cosmetic? Or, are there fundamental business and IP distinctions? These and other questions will be discussed as the panel examines the future of the designer -- ASIC vendor -- EDA vendor relationship. WHO: Panel Members -- Tommy Eng -- president and CEO of Tera Systems, Inc., Campbell, CA -- Tom Russell -- IBM Microelectronics, Essex Junction, VT -- Kazu Yamada -- NEC Corp., Santa Clara, CA -- Sandeep Khanna -- Synopsys, Inc., Mountain View, CA -- Kamalesh Ruparel -- Cisco Systems, Inc., Saratoga, CA WHEN: Wednesday, June 12, 2002, 10:30 AM - 12:00 PM (Session 22) WHERE: Auditorium A at the Ernest N. Morial Convention Center, New Orleans during the 39th annual Design Automation Conference (DAC) June 10th - 14th. For more information visit the DAC web site at: www.dac.com. About Tera Systems Tera Systems, Inc. is the leader in Hardware Description Language (language) Hardware Description Language - (HDL) A kind of language used for the conceptual design of integrated circuits. Examples are VHDL and Verilog. (HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. )-based design planning technology for use by designers of complex System-on-Chip See SoC. (SoC) semiconductors. The company's products provide early visibility into design quality, performance, and manufacturability issues with the goal of preventing downstream From the provider to the customer. Downloading files and Web pages from the Internet is the downstream side. The upstream is from the customer to the provider (requesting a Web page, sending e-mail, etc.). problems with synthesis and physical design processes. Using the Tera Systems tools, SoC designers can ensure timing convergence and superior performance before reaching back-end (programming) back-end - Any software performing either the final stage in a process, or a task not apparent to the user. A common usage is in a compiler. A compiler's back-end generates machine language and performs optimisations specific to the machine's architecture. layout or actual silicon where the costs of design errors or changes are extraordinarily high. Tera Systems partners with leading semiconductor vendors to develop highly predictable design methodologies and "golden" tool flows that dramatically accelerate the SoC design cycle. For more information, visit our web site at www.terasystems.com. |
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