ADVISORY/Real Intent Presentation at DVCon: Designing Safe Multi-Clock Chips with Clock Intent Verification; Tuesday, March 2, 2004, 2:00-2:30 p.m.Business Editors/High-Tech Writers ADVISORY...for Tuesday (March 2) DVCon SANTA CLARA Santa Clara, city, Cuba Santa Clara (sän`tä klä`rä), city (1994 est. pop. 217,000), capital of Villa Clara prov., central Cuba. , Calif.--(BUSINESS WIRE)--Feb. 27, 2004
Who
Real Intent Inc. of Santa Clara, California, the leading supplier
of formal Assertion-Based Verification (ABV) software for
Block-to-Chip-level electronic-system design
What
DVCon (Session 4) - Overcoming Challenging Verification Issues
Designing a Safe Multi-Clock Chip with Clock Intent Verification,
Jay Littlefield, Director of Application Engineering, Real Intent
Few areas of chip design are fraught with peril as multiple,
asynchronous clocks. A better solution, including automatic
assertions and formal verification techniques, is available today
to ensure that multi-clock designs are fully verified prior to
tape out. Attend this talk to understand how our product Verix can
easily verify meta-stability, loss of correlation, data
instability and improper reset synchronizations issues that are
very hard to verify using traditional testbench methodologies.
When: Tuesday, March 2, 2004, 2:00-2:30 p.m.
Where
DVCon, Doubletree San Jose, 2050 Gateway Place, San Jose, CA
95110-1047
Information and Registration For more information about Real Intent, please visit www.realintnet.com. For DVCon information and registration, please visit www.dvcon.com. About Real Intent's Verix Verix is Real Intent's assertion-driven formal verification
In the context of hardware and software systems, formal verification system for exhaustively verifying that a design is free from complex, corner case errors that are hard to catch in simulations. Verix is easily deployable because of its automatic setup and built-in assertions. A suite of highly tuned formal verification engines, combined with a patented hierarchical formal verification, gives Verix the highest capacity in the industry. It supports Accellera's Open Verification Library Open Verification Library (OVL) is a library of property checkers for digital circuit descriptions written in popular Hardware Description Languages (HDLs). OVL is currently maintained by Accellera. (OVL OVL Oval (street type) OVL Open Verification Library OVL Program Overlay (File Name Extension) OVL Oxford Vehicle Leasing (UK) OVL Officier Vlieger ) and Property Specification Language (PSL 1. PSL - Portable Standard Lisp. 2. PSL - Problem Statement Language. See PSL/PSA. ) standards, as well as the IEEE (Institute of Electrical and Electronics Engineers, New York, www.ieee.org) A membership organization that includes engineers, scientists and students in electronics and allied fields. standards for Verilog and VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. . About Real Intent Real Intent offers assertion-based formal verification products for electronic design. Its products are deployed at several leading semiconductor design companies in North America North America, third largest continent (1990 est. pop. 365,000,000), c.9,400,000 sq mi (24,346,000 sq km), the northern of the two continents of the Western Hemisphere. , Japan and Europe. These products offer users the capability of comprehensive design verification early in the design process and significantly reduce the cost of verifying integrated circuits, electronic systems and systems on a chip. Real Intent is located at 3910 Freedom Circle, Suite 102A, Santa Clara, CA 95054, tel.: 408-982-5444, fax: 408-982-5443, email: info@realintent.com, web: http://www.realintent.com. Verix is a trademark of Real Intent Inc. All other trademarks and tradenames are the property of their respective owners. |
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