ADVISORY/DAC Advisory For @HDL - Seminar Series Announcement.News Editors/High-Tech Writers ADVISORY...for Monday-Thursday (June 2-5) Design Automation Conference 2003 Booth #2160 --(BUSINESS WIRE) @HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. , Incorporated, an Electronic Design Automation (EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. ) company focused on accelerating functional verification Functional verification, in electronic design automation, is the task of verifying that the logic design conforms to specification. In everyday terms, functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a complex task, , is pleased to announce a special series of technical presentations and seminars at the upcoming Design Automation Conference, DAC See D/A converter and discretionary access control. DAC - Digital to Analog Converter , next week in Anaheim, California “Anaheim” redirects here. For Annaheim, see Annaheim, Saskatchewan. Anaheim is a city in Orange County, California, located 28 miles southeast of Los Angeles. , June 2 through June 5. DAC BOOTH INFORMATION: The @HDL DAC booth, #2160, will have hourly product demonstrations of the newest versions of @Verifier-DP and @Designer. The @Verifier and @Designer products incorporate formal verification and analysis, combined with extensive simulation, assertion and testbench debugging capabilities. These products provide a unique solution for assertion-based verification, supporting both the PSL 1. PSL - Portable Standard Lisp. 2. PSL - Problem Statement Language. See PSL/PSA. Sugar and OpenVera Assertion languages. SPECIAL DEMO SUITE PRESENTATIONS: @HDL will be unveiling major new products at the @HDL Demo Suite, #2482. Advanced registration is available at the company website, www.atHDL.com. Twice daily 45-minute Demo Suite Seminars, Monday, Tuesday and Wednesday, June 2-4, covering a sneak preview of the new @HDL products being introduced at DAC include: Seminar I: @Verifier-ZX -- Breakthrough Formal Verification and Analysis with PSL/Sugar Come see a new generation of high-performance, high capacity formal verification and analysis products. @HDL is collaborating with IBM (International Business Machines Corporation, Armonk, NY, www.ibm.com) The world's largest computer company. IBM's product lines include the S/390 mainframes (zSeries), AS/400 midrange business systems (iSeries), RS/6000 workstations and servers (pSeries), Intel-based servers (xSeries) , and has licensed IBM's premium formal verification technology. The result of this collaboration is a breakthrough functional verification solution, combining the @HDL pioneering formal design analysis and debugging technology with IBM's high-performance formal verification engines. More details about the collaboration are on the @HDL website, www.atHDL.com. Seminar II: Accelerating Design Verification with new @HDL Testbench products @HDL will be unveiling major new products in the area of testbench automation, including @Verifier-DCS -- an automatic, block-level functional vector generator, which incorporates intelligent functional vector generation through advanced techniques in formal model checking, assertion-based verification and constraint specification. This seminar will also include a sneak preview of a new high performance testbench simulator from @HDL, supporting an industry standard testbench language. |
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