ADVISORY/Accellera Hosts SystemVerilog Symposium and Vendor Fair in Silicon Valley; Thursday, December 4, 2003, Santa Clara, California.Business Editors/High-Tech Writers ADVISORY...for Thurs. (Dec. 4) --(BUSINESS WIRE) Accellera Who Accellera, the EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. organization focused on language-based design standards Design standards Specifications of materials, physical measurements, processes, performance of products, and characteristics of services rendered. Design standards may be established by individual manufacturers, trade associations, and national or , invites the electronic design community to attend a SystemVerilog Symposium and EDA Vendor Fair in Santa Clara, California Santa Clara, California (IPA: /ˌsæntəˈklærə/) , founded in 1777 and incorporated in 1852, is a city in Santa Clara County, in the U.S. state of California. What Accellera's SystemVerilog Symposium features two tracks, lunch and an EDA Vendor Fair Track I: SystemVerilog Basic Training SystemVerilog language extensions will be presented in a designer-centric fashion by Verilog design expert, Cliff Cummings of Sunburst Design, Inc. This highly technical event will demonstrate how advanced features of SystemVerilog can now be used to increase design and verification productivity, improve design quality and reduce time-to-market pressures. Track II: SystemVerilog Product Technology Track This track is a set of presentations from leading electronic design automation solution suppliers that give in-depth technical insight into how their products leverage the SystemVerilog standard. Topics will include synthesis, assertions, acceleration, emulation, debugging and integration of co-simulation using the Direct Procedural Interface (DPI (Dots Per Inch) The measurement of the resolution of display and printing systems. A typical CRT screen provides 96 dpi, which provides 9,216 dots per square inch (96x96). Flat panel displays from 110 to 200 dpi have also been developed. ). Accellera committee members will present updates on current SystemVerilog activities. Lunch will be served during this session. EDA Vendor Fair This is a 2-hour event during which participating companies will demonstrate their SystemVerilog-based products and be available to discuss their SystemVerilog support. Accellera Technical Chair Members will also be available for private discussions. Demos of SystemVerilog-based tools from leading EDA companies  The external links in this article or section may require cleanup to comply with Wikipedia's content policies. including Accellera
members Axis Systems, Cadence, Mentor Graphics Mentor Graphics, Inc (NASDAQ: MENT) is a US-based multinational corporation dealing in electronic design automation (EDA) for electrical engineering and electronics, as of 2004, ranked third in the EDA industry it helped create. , Novas, Real Intent and
Synopsys among others are featured.
When 8:15 a.m.-3:30 p.m., Thursday, December 4th, 2003 Where Santa Clara Santa Clara, city, Cuba Santa Clara (sän`tä klä`rä), city (1994 est. pop. 217,000), capital of Villa Clara prov., central Cuba. Marriott, 2700 Mission College Blvd., Santa Clara, CA 95054 Agenda 8:15 a.m. - 9:00 a.m. Registration and Continental Breakfast 9:00 a.m. - 11:30 p.m. Track I: SystemVerilog Basic Training Track II: SystemVerilog Product Technology Track 11:30 a.m. - 1:30 p.m. Lunch and Accellera SystemVerilog Update 1:30 p.m. - 3:30 p.m. EDA Vendor Fair Information and Registration Please visit http://www.systemverilog.org/events/sv_symposium03.html for more information, and to register. About SystemVerilog SystemVerilog evolves the Verilog hardware description language (language) Hardware Description Language - (HDL) A kind of language used for the conceptual design of integrated circuits. Examples are VHDL and Verilog. (HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. ) with powerful design and verification capabilities. It provides design constructs for architectural, algorithmic and transaction-based modeling. It adds an environment for automated testbench generation, while providing assertions to describe design functionality, including complex protocols, to drive verification using simulation or formal verification techniques. Its C-API (Application Programming Interface) provides the ability to mix Verilog and C/C C/C Center to Center C/C Combustion Chamber C/C Command/Control C/C Crew Chief C/C cabin cruiser (US DoD) C/C chief complaint (medical) C/C Channel-to-Channel C/C Communication and Collaboration ++ constructs. About Accellera Accellera is an electronics industry organization driving the worldwide development and use of standards required by systems, semiconductor, and design tools companies that enhance a language-based design automation process. For more information, please visit www.accellera.org. All trademarks and tradenames are the property of their respective holders. |
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