ADVISORY/@HDL to Host Seminar Series at DAC; Announcing ''Find more bugs, Faster'' Seminars and On-line Product Demo Availability.Business Editors/High-Tech Writers ADVISORY...for Monday-Wednesday (June 7-9) Design Automation Conference 2004 MILPITAS, Calif.--(BUSINESS WIRE)--May 26, 2004 @HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. , Incorporated
WHO: @HDL, Incorporated, a leading supplier of electronic design
automation software for the functional verification of complex
semiconductor devices.
WHAT: You are invited to attend the @HDL "Find more bugs, Faster"
Seminars being held at the Design Automation Conference (DAC), Booth
#3943, San Diego Convention Center. @HDL will be exhibiting at the
conference, presenting technical details of our functional
verification product families.
@HDL is pleased to announce immediate availability of web-based,
multimedia product demonstrations of the powerful features included
with our @Verifier and @Designer-PRO products. Point your browser to
http://www.atHDL.com/demosondemand and experience for yourself how
@HDL can help improve your functional verification productivity.
Come see why @HDL has emerged as the technology leader in advanced,
assertion-based functional verification, delivering PSL and
SystemVerilog. Find more bugs faster during RTL development -- with
automatic model checking, extensive multiple clock domain
verification/analysis and tight integration with simulation.
WHEN: The Design Automation Conference, (DAC), is being held Monday
through Thursday, June 7-10, 2004. Exhibit hours can be found on the
DAC website, www.dac.com.
SEMINAR DETAILS: The "Find More Bugs, Faster" seminars will be held at
the @HDL Demo Suite, adjacent to our DAC Booth, #3943. These twice
daily 45-minute seminars, Monday, Tuesday and Wednesday, June 7, 8 and
9, will cover a preview of new products being introduced this year by
@HDL. Registration for the seminars can be done through the @HDL
website, www.atHDL.com.
Seminar 1: Monday, Tuesday, Wednesday: 11:00 to 11:45 AM
-- @HDL SystemVerilog Product Introductions -- A New generation of
High-performance, High Capacity Functional Verification and
Analysis products
Seminar 2: Monday, Tuesday, Wednesday: 3:00 to 3:45 PM
-- @Verifier-ZX / Release 4.5 -- Joint IBM and @HDL technical seminar
covering the updated collaboration efforts between IBM formal
experts delivering Rulebase PE and the @HDL formal verification
engineering team.
About @HDL @HDL is an electronic design automation (EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. ) company focused on accelerating functional verification of SoC and silicon IP designs. The @Verifier, @Verifier-DP, @Verifier-ZX, @Designer and @Designer-PRO products deliver significant verification productivity improvement, through system-level design analysis and debugging, automatic formal model checking, and tight integration with existing RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; simulation environments. Supporting both the Accellera PSL 1. PSL - Portable Standard Lisp. 2. PSL - Problem Statement Language. See PSL/PSA. and SystemVerilog assertion languages, @HDL delivers an effective assertion-based verification product suite to its customers, including such companies as Azul, Ambarella am·ba·rel·la n. In both senses also called Otaheite apple. 1. A tree (Spondias cytherea) native to the Pacific islands and grown in tropical and subtropical regions for its edible fruits. 2. , Cisco, Fujitsu, OKI Semiconductor, SiNett, Raza Microelectronics, Renesas and Toshiba. @HDL is a member of the Cadence (NYSE NYSE See: New York Stock Exchange :CDN (Content Delivery Network) A system of distributed content on a large intranet or the public Internet in which copies of content are replicated and cached throughout the network. ) Connections Program, the Mentor Graphics (NASDAQ NASDAQ in full National Association of Securities Dealers Automated Quotations U.S. market for over-the-counter securities. Established in 1971 by the National Association of Securities Dealers (NASD), NASDAQ is an automated quotation system that reports on :MENT) Value Added Partners program and the Synopsys (NASDAQ:SNPS SNPS Space Nuclear Power System ) in-Sync Program. For more information, call 408-433-9997, visit www.atHDL.com or email to info@atHDL.com. |
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