ACAD releases FineSim hybrid simulation analysis tool.ACAD ACAD Academy ACAD Academic ACAD AutoCAD (design/drafting development software by Autodesk) ACAD Acadia National Park (US National Park Service) ACAD Atherosclerotic Coronary Artery Disease Corporation has announced the introduction of FineSim, a hybrid simulation analysis tool that incorporates transistor-level simulation analysis capabilities for mixed digital and analog design. FineSim can achieve SPICE-level accuracy with the most demanding analog design blocks while delivering high performance. In addition, FineSim can be used for full chip analysis at both pre- and post-layout stages while maintaining full transistor-level accuracy. FineSim was developed based on a highly-accurate full chip transistor-level turbo SPICE simulation algorithm, with the option of an embedded HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. engine for Verilog and VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. . Additional options include the support of non-ideal power analysis and dynamic RC reduction algorithms for signal and power nets. "We designed FineSim in response to the needs of our key customers," said Andy Huang, President and CEO (1) (Chief Executive Officer) The highest individual in command of an organization. Typically the president of the company, the CEO reports to the Chairman of the Board. of ACAD, "FineSim is a complete suite of tools that enables our customers to easily verify the functions and timing of advanced LSI LSI: see integrated circuit. (Large Scale Integration) Between 3,000 and 100,000 transistors on a chip. See SSI, MSI, VLSI and ULSI. designs." Both Volatile and Non-Volatile memory IC are essential for today's computing, consumer, telecom, and networking applications, and FineSim has been used in these applications. The challenge of memory design verification involves accuracy for high analog blocks, high performance for access time verification, and full chip capacity for functional verification. Using FineSim, one of ACAD's 256M memory design customers completed its full chip post-layout simulation within 24 CPU CPU in full central processing unit Principal component of a digital computer, composed of a control unit, an instruction-decoding unit, and an arithmetic-logic unit. hours, and was able to uncover design bugs that were not found previously with other EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. vendor tools. The design team is now preparing to use FineSim in their next generation memory design, with larger memory capacity and much faster clock speed on their most advanced process. Today's designers face the challenges of accurately simulating mixed digital and analog at the block level and accurately simulating soft and hard IPs at the full chip level. FineSim addresses these challenges with full transistor-level simulation. In addition, designers have to face the challenge of reduced noise margins due to lower supply voltage. FineSim's hybrid simulation technology addresses this challenge by providing all the key functions that designers need at various stages of the design. |
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