A novel low CTE, high stiffness ceramic composite core: a new substrate demonstrates superior results under accelerated thermal cycle test and finite element modeling.

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A novel ceramic composite board material, C-SiC, addresses the need for ultra-high-density multilayer wiring to route high I/O counts, enable reliable Cu-low k ICs and also provide reliable fine-pitch interconnections between the IC and package. An integrated SOP package with embedded components and digital, RF and optical functions requires ultra-low-loss, low-stress, high-strength dielectrics that have stable electrical properties over a wide range of frequency and temperature.

Experimental results were corroborated with FEM modeling results. The high stiffness C-SiC boards with thinner BCB dielectrics did not show failures related to dielectric cracking or solder joint fatigue. While finer via diameters could aggravate the microvia strains, a combination of low CTE and high-strength dielectrics can address the reliability problem in multilayered structures. The proposed high-performance ceramic composite substrate material in combination with ultra-low-loss dielectrics showed the required attributes for solder joint reliability, dielectric reliability, low warpage and microvia reliability for the fabricated two-metal layer system. C-SiC boards also exhibit low via-pad misregistration, making them suitable for building multilayered structures on a larger area with smaller via capture pads. In addition, the manufacturability of these boards enables them to be cost-effectively produced in large volumes. These boards have the potential to be the ideal candidate board materials for next-generation high-density packaging requirements.

Nitesh Kumbhat, P. Markondeya Raj, Raghuram V. Pucha, Venky Sundaram, S. Sitaraman and Rao R. Tummala are with the Georgia Institute of Technology (Georgia Tech) Packaging Research Center (gatech.edu). Contact Raj at [e-mail]. Ed Bongio is with Starfire Systems Inc.

Nitesh Kumbhat, P. Markondeya Raj*, Raghuram V. Pucha, Venky Sundaram, Ed Bongio, S. Sitaraman and Rao R. Tummala

Table 2. Thermal Shock Experimental Results

Substrate
(CTE ppm/       Dielectric
[degrees]C      (CTE ppm/[degrees]C  Thickness for       Cycles to
Modulus GPa)    Modulus GPa)         Buildup ([micro]m)  to Failure

FR-4 (17, 20)   Epoxy (60, 3.5)      60-70                <100
C-SiC (2, 150)  Epoxy (60, 3.5)      60-70                 500
C-SiC (2, 150)  BCB (45, 2.5)         5-10               >1000
C-SiC (2, 150)  PPE (15, 2.4)        30                  >1000
C-SiC (2, 150)  Polyimide (60, 2.5)  60                  >1000

Substrate
(CTE ppm/
[degrees]C
Modulus GPa)    Primary Failure Mode

FR-4 (17, 20)   Solder-joint cracking
C-SiC (2, 150)  Dielectric cracking; copper line cracking
C-SiC (2, 150)  None
C-SiC (2, 150)  None
C-SiC (2, 150)  None