A new, thin high-performance organic substrate: the flip-chip package can be conventionally processed and meets lead-free demands.

Ed.: For the full article, please see circuitsassembly.com/online/0501/0501_3m.shtml. This paper is courtesy of the SMTA (smta.org).

Advanced semiconductor package development has been driven by electrical performance improvements, breakthroughs in silicon technology, higher pin counts and more efficient real estate usage. High-performance IC packages have migrated from peripherally bonded designs to area array flip-chip configurations. Flip-chip technology and ball grid arrays permit a chip I/O count of several thousands in usable density to the PCB. Increased bandwidth and functionality forces development of a substrate technology to meet the need for fast data rate transfer in an effective package. The trend toward copper metallization and low-K dielectrics for 90 nm (and lower) silicon technologies is testing the limits of conventional packaging. Thinner core (or coreless) substrates provide superior electrical performance in demanding system applications. These packages must exhibit a high level of package robustness and show flip chip solder joint reliability through both package- and board-level reliability tests. (1) A new organic flip-chip package substrate is being ramped into production. This laminated substrate technology uses an engineered composite dielectric combined with advanced fabrication techniques to produce very high-density organic substrates.

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In organic flip-chip packages, many of the most critical reliability attributes are related to die size and package construction. CTE mismatch between the die and laminate leads to relative displacement during testing and under use conditions that eventually cause solder joint failures. Die size plays a major role in determining the maximum principal stresses in a finished package. Underfill mitigates the effect induced by the CTE mismatch between the die and the substrate. It also provides physical protection for the solder joints. Recent work confirms that low-modulus underfill materials can minimize die area stress and reduce the incidence of many different flip chip package failure modes. (2) Substrate material properties, layer count, substrate thickness and even the metallization pattern on individual layers also affect the stress condition and, therefore, reliability. Stress conditions also cause package warpage or nonflatness. Excessive package warp can negatively influence flip chip solder joint quality and reliability, as well as BGA solder joint yield and reliability. New packaging materials and processes are currently being demonstrated. (3)

Two new dielectric materials have been developed to meet the needs for improved via and signal trace density, improved electrical performance and reduced cost. A thin embedded capacitance material may be used as the core of the new substrate. Also, a new dielectric material with superior electrical and mechanical properties makes up the remainder of the dielectric in the substrate cross-section.

The embedded capacitance material is an 8 [micro]m thick thermosetting resin, filled with a high dielectric constant ceramic, which is sandwiched between 18 [micro]m copper sheets. Used in the core of the new substrate, this material is ideal for high frequency decoupling, can eliminate the need for discrete chip capacitors and dampens voltage ripple and plane resonances. (4) Based on the same coating technology used to make the embedded capacitor material, the new dielectric material is a thin (30 [micro]m) thermosetting resin with ceramic filler added to modify the material's mechanical properties. Of note are the low dielectric constant (3.2), and loss (0.002). The addition of filler to the resin reduces the z-axis CTE to 32 ppm/[degrees]C, permitting the use of small, laser-drilled, plated-copper vias in the substrate. An unfilled material would result in CTE mismatch-driven via wall fatigue cracks during thermal cycling. The material behaves over a range of frequencies. It is also environmentally friendly: The high Tg makes the substrate suited for no-lead solder reflow, and the material contains no halogens.

Though several cross-sectional variations are possible, the most typical construction consists of eight metal layers and does not require soldermark.

The advanced dielectric materials, thin core-construction, laser-drilled microvias and fine-pitch circuitry provide, in combination, a high-performance chip package substrate capable of supporting large die at full array 180 [micro]m flip chip pitch. Table 1 shows modeled electrical and density performance comparisons to a typical 500 [micro]m core pitch 3-2-3 build-up chip package substrate with a sgs-gp-sps construction. Routing is improved through a combination of fine-pitch circuitization and 200 [micro]m core via pitch.

Balanced Design

The typical large die flip chip package assembly process consists of several steps: 1) flip chip die flux and place, 2) solder bump reflow, 3) underfill and cure, 4) heat spreader/lid attach and cure, 5) BGA ball attach and reflow. The substrate's metal stiffener must be properly designed to ensure the flattest assembly. Controlling substrate warp at room temperature is needed for accurate die placement. Controlling substrate warp above solder reflow temperature is critical for proper solder joint formation. Defective solder joints, such as bridged solder balls or malformed solder joints, can result from uncontrolled substrate warp. Organic substrate flatness specifications are typically in the 100 to 150 [micro]m range. In the die area, the substrate must be flatter yet.

By measuring nonflatness as a function of temperature, the authors found that substrate warp can be influenced by stiffener geometry, substrate and stiffener thickness, modulus, CTE, type of stiffener adhesive and bonding conditions, moisture absorption or desorption, and other factors as well. A slight difference in CTE between the organic substrate and the metal stiffener will create substrate warp in response to temperature changes. Successful assembly relies on detailed understanding and good management of the most influential factors. (5)

A flatter substrate was produced by balancing the substrate design and improving the stiffener attach manufacturing process. Then a successful assembly process was validated on a 45 mm substrate with 19 mm die using an industry-standard reflow profile, optimized flux and underfill and minor tooling changes.

Package-level reliability testing is now in process, using both an eight-metal layer 40 X 40 mm test vehicle designed for a 10.6 X 12 mm die, and an eight-metal layer 45 X 45 mm test vehicle designed to accommodate a large 19 X 19 mm die.

Both dies are stitch configurations, with approximately 900 flip chip pads on a 240 [micro]m pitch in the smaller die, and almost 9000 flip chip pads on a 200 [micro]m pitch on the large die. Both test vehicles are furnished with structures intended to stress the highest density design rules of the technology, and contain chains of blind and buried vias, long lengths of parallel trace of 20 [micro]m width/30 [micro]m space intended for biased humidity testing, and large buried capacitance structures for the same purpose. Among the tests was resistance change of three testable flip chip nets on 36 samples after 500 air-to-air thermal cycles. The test reject limit of 10% was never approached.

TABLE 1: Performance and density comparison.

Parameter                             New Substrate  3-2-3 Buildup

Core thickness ([micro]m)                   8             500

Estimated power distribution              0.47           0.70
impedance (1 GHz)

Vertically distributed power              0.91           2.20
distribution impedance (1 GHz)

Crosstalk (% @ 2.5V, 200ps risetime,       <1%            <1%
25 mm coupling, 2x aggressor lines,
100 [micro]m pitch)

Routing (signals per column at 200        10.5            6.4
[micro]m effective flip-chip pitch)

Donald Banks, Robin Gorrell, Duy Le-Huu, David Hanson and Shichun Qu are with 3M (mmm.com); [e-mail].