A matter of timing: gone are the days when chip delays consumed the bulk of overall timing budgets. Now, board-level timing margins are more important than ever.

Not long ago, timing wasn't that big an issue on most PCB designs. But the large timing margins that designers once took for granted have been consumed by a reduction of die sizes and component geometries, which have dramatically decreased the propagation delays through these devices. This has virtually eliminated timing margins, which were once sufficient in most cases.

With this trend has come a dramatic increase in clock rates used at board level. While the technologies for creating the majority of PCBs have remained mostly unchanged despite the adoption of many manufacturing innovations, the decrease in interconnect delays due to board size has not kept pace with the decreases from the shrinking die sizes and increased clock speeds prevalent in many components used today. As a result, board-level interconnect delays account for a much larger percentage of the overall timing budget, resulting in a dramatic decrease in the overall timing margins of designs.

Designers can no longer rely on traditional rules of thumb for high-speed design. More formal methods are needed to ensure reliable design operation at intended speeds under all conditions, taking into consideration such issues as circuit timing problems, timing variations and false timing violations.

Many designers are at least aware of the signal integrity problems they may encounter in their designs. But traditionally, these problems were observed primarily in the analog effects of signal integrity, and too often this is the only side considered in the design.

Engineers often neglect to consider the digital side of the signal integrity problem: timing. A complete analysis consists of taking both digital timing (digital) and signal integrity (analog) issues into account. Three questions must be considered in relation to circuit timing: 1) How are timing problems found? 2) How are timing problems fixed? 3) How are timing problems prevented?

Typically, these circuit timing problems are associated with device selection, logic design or interconnect delays. Timing problems are often detected either at post-layout or after product deployment. These detection methods have one thing in common: they find circuit timing problems after the design has been completed. Consequently, the later in the product development cycle these problems are identified, the greater the cost, not only in design rework, but in financial and other less tangible expenses as well. The design phase is the best time to fix timing problems. Essentially, this involves correcting the design by selecting components with different timing settings or augmenting circuit functionality to resolve timing problems. Today's timing analysis and verification tools effectively allow designers to find and eliminate timing problems in their designs.

High-frequency clocks are not the only cause of timing problems. Introducing aggressive timing constraints can also affect the stability of the design. Symbolic timing analysis addresses the need to verify board-level timing and easily manages design changes for revalidation or analysis. Before symbolic timing analysis can be discussed, the following areas must be addressed: timing models, timing and functional behavior, timing variations, and different timing solutions.

Timing Models

Timing information is available from a number of different sources, including datasheets, Timing Diagram Markup Language (TDML) and STAMP. Produced by the component vendors and available in both electronic (PDF) and print format, datasheets are by far the most widely available source of component timing information.

TDML is an electronic waveform standard that is based on extensible markup language (XML). TDML models expedite timing analysis, as component information is readily available in a machine-readable format. In essence, TDML contains datasheet information in an electronic format that features graphical waveforms, allowing timing relationships between the waveforms to be viewed and edited.

STAMP is an electronic format that is generally used for timing analysis in conjunction with FPGA and ASIC design tools. STAMP provides a mechanism for describing timing paths (arcs), and it associates timing numbers to each of these timing paths. Although the STAMP format is not an open standard, it is considered a stable and viable format for expressing component timing. Models are described in two parts: model file (timing arcs) and data file (timing numbers). Functional model information is not provided in the STAMP format.

In addition, multiple data files may be overlaid onto a single model file. This is beneficial when using custom or programmable devices that have one functional description and may have multiple timing versions from different places and routes.

Both TDML and STAMP models provide an electronic format for determining timing errors in various components. With complex components, simple assumptions about device behavior can't be inferred from timing waveforms. In these cases, both the timing and the bus interface functional behavior is of interest to the designer; the internal workings of the component are irrelevant.

Components with phase lock loops (PLL) and other reclocking schemes, and devices controlled by incoming electrical signals (such as memory devices using RAS/CAS) are readily described by their bus interface functional behavior. The high-level bus functional information that describes how a device interacts with other devices allows symbolic timing analysis to eliminate false timing paths during timing analysis.

Timing Variations

Components used throughout the design process are typically representative of a small sampling of the parts available when the design goes into production. As a result, designers see only a small window of delay variation as we progress through the design process. See FIGURE 2. But as the design enters the manufacturing phase and eventual deployment in the field, the full spread of component-timing variations become apparent. Since the same manufacturer often produces many components used at the design's prototype stage, the devices physically used early in the design cycle may not represent the complete timing spread of all components. Consequently, it becomes imperative that a broad timing spread of available components be represented during analysis of the design.

[FIGURE 2 OMITTED]

There are a number of traditional ways designers can resolve timing issues within their designs, including manual methods, timing waveform, static timing analysis, fully functional simulators and clock path analysis. Manual timing methods (hand calculations) are useful on small designs with simple circuits. But these methods tend to break down with larger designs, and there can be difficulties with partitioning clock domains. Microsoft Excel spreadsheets are primarily used to automate the timing calculation process. However, subtle design changes, particularly with net connectivity, may alter the timing calculations, making it a challenge to keep the design and the timing calculations synchronized.

With timing waveform, component waveforms are connected with timing delays that represent the net connectivity of the design. The timing delays represented in these waveforms are used to approximate the actual interconnects in the design. Manually creating waveforms to represent the design netlist often limits the reuse of timing constraints in subsequent designs and creates a significant synchronization burden when design edits are made.

Static timing analysis is widely used in the ASIC space, and it is a commonly used verification method for synchronous repeated logic. The models used in this method generally do not contain any functional information about the components in the design. False timing paths are often evaluated, resulting in reports of false violations during static timing analysis. The timing tool produces false timing violations by traversing signal paths that would not normally occur. For example, the functional effects of signals like _OE (Output Enable) or _CS (Chip Select) are not considered.

Fully functional simulators are powerful simulation methods that enable engineers to validate the correct behavior of their designs. These simulations require complex functional models and have very long run times. They produce accurate simulations for a given set of input stimulus. However, the results for timing produced from a fully functional simulation consider only a parametric view of timing, and entire device timing spreads are not considered during a single simulation run. Test vectors are often required to stimulate the design and verify correct functional behavior. These golden results are often the product of many hours of interactive work by an engineer and valid only for a specific design. Design changes may require re-verification of test vectors to ensure adequate coverage.

Correct analysis of clock paths through a design is a very important part of timing analysis. As data paths traverse the design through clocked components, careful attention must be paid to the signal paths, the origin of the clocks and the way the data paths traverse the design with respect to data and control signals. Source synchronous devices have heightened the importance of accurate clock analysis, particularly since they tend to be an integral part of today's more advanced chipsets and memory architectures.

Symbolic timing models extend the available static timing models to include bus functional information. Timing information from TDML, STAMP or component vendor datasheets is augmented with sufficient functional information to differentiate timing. Functional behavior is derived from the logical description of the device, the datasheets, or even implied with the device timing. However, a full behavioral description of the device is not required. Only the bus interface is needed. Functional behavior for the device is required so that false timing paths are avoided.

False Violations

FIGURE 3 illustrates why static timing analysis may report false violations on a board-level circuit. Here, the verification of the setup time on the data input of a memory controller is relative to Write Enable (WE). This constraint is important during the write access to SRAM.

[FIGURE 3 OMITTED]

Static timing analysis traces paths through a circuit. To verify this constraint, the maximum delay path to I/O and the minimum delay path to WE is traced. Both of these paths originate at the clock signal of the memory controller. Using typical delay values, the maximum delay to I/O is 13 nsec, and the minimum delay to WE is 5 nsec. Static timing analysis has established that instead of arriving 12 nsec before (20 +5 -13) WE (at the next clock edge), I/O actually reaches 8 nsec after (5 -13) WE (on the same clock edge). Therefore, the setup time is violated and the slack is -15 nsec (-8 -7). When such a large violation is reported in a fairly straightforward design, engineers tend to question the validity of the assumptions made by the timing and analysis tool.

In this case, an erroneous assumption is made that both I/O and WE transition relative to the same clock edge. For a write cycle, that data is typically pushed out by a controller and one clock cycle later WE rises, indicating the end of a write access. When this behavior is considered, the constraint is technically satisfied. For this reason, accurate board timing verification requires information on the read/write cycles of components.

Some static timing tools allow this multicycle behavior to be described on a design-by-design basis. This requires that the engineer uniquely identify each of these behaviors in each new version of the design. At best this is a laborious task, relying on the due diligence of the engineer for coverage of all component interactions. The static timing models do not contain this valuable information, which is essential for repeatable and accurate timing analysis.

Symbolic timing analysis provides designers with a more appealing solution for circuit timing analysis than either static timing verification or functional simulation. Symbolic timing analysis tools offer analysis speeds comparable to static timing, but without reporting false timing paths. Much like static timing, symbolic timing uses simple timing models. However, the functional information used to differentiate timing is unique to symbolic timing analysis.

Symbolic timing analysis does not require the test vectors of functional analysis to exercise the circuit, thus eliminating incomplete timing coverage due to incomplete vector coverage. The complete spread of timing, not just a parametric window, is considered for all devices. Symbolic timing performs the worst-case timing analysis and verification, and is designed for board-level analysis.

Utilizing a circuit netlist and timing models, symbolic timing analysis may occur up-front in the design process, or as a verification tool towards the end of the design cycle. Symbolic timing analysis (digital timing) and signal integrity analysis (analog interconnect effects) are used together to provide a complete timing solution, including signal interconnect delays and signal integrity effects.

FIGURE 4 shows a complete design flow that uses both symbolic timing analysis and signal integrity analysis. Industry standards are used for both the signal integrity and timing component models.

[FIGURE 4 OMITTED]

IBIS, SPICE or VHDL-AMS are used for signal integrity analysis. Symbolic timing models may be created using device datasheets, TDML, STAMP and other electronic source models.

Incorporating accurate timing margins under extreme conditions and understanding specific timing sensitivities in the circuit ensures robust system operation. Eliminating timing problems early in the design cycle reduces, and may even eliminate, multiple design iterations and costly rework.

Further, exploring device timing alternatives allows for the most effective combination of devices while ensuring that the design still meets performance goals. The use of circuit netlists with symbolic timing models provides a repeatable mechanism that easily accommodates circuit connectivity changes, explores device variations and guarantees correct net connectivity during analysis.

Symbolic timing allows circuit designers to explore, understand and validate the timing requirements of a circuit. These requirements can drive physical routing to provide a complete solution for timing.

MATTHEW HOGAN is a technical marketing engineer for Mentor Graphics Corp. He has over 10 years of design and field experience. Hogan can be reached at [e-mail].