@HDL Releases Enhanced Version of Verilog Debugging Tool; @Designer Available From Website for Downloading With- Special Limited-Time, Pricing Offer.Business Editors/High-Tech Writers SAN JOSE, Calif.--(BUSINESS WIRE)--Dec. 10, 2001 @HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. , Inc. today announced the release of @Designer version 2.1, delivering a new standard of functionality for the graphical debugging and design analysis stages of System-on-Chip (SOC) design. @Designer now supports the leading Verilog simulators, including NC-Verilog and Verilog-XL from Cadence (NYSE NYSE See: New York Stock Exchange :CDN (Content Delivery Network) A system of distributed content on a large intranet or the public Internet in which copies of content are replicated and cached throughout the network. ), Modelsim from Mentor Graphics (Nasdaq:MENT), and VCS (1) (Verilog Computer Simulator) See Verilog. (2) (Version Control System) See version control. from Synopsys (Nasdaq:SNPS SNPS Space Nuclear Power System ). SOC design teams can take advantage of the unique capabilities now available in @Designer to significantly improve their verification productivity. @Designer 2.1 includes powerful new features not currently provided in other commercially available products. With @Designer both verification and design engineers can now carryout car·ry·out adj. Intended to be consumed away from the place of sale; takeout: a shop offering carryout sandwiches. n. An item of food or a meal that is to be consumed away from the place of sale. extensive Verilog simulation post-processing, including: -- Execution Tracing, identifying the lines of RTL code being evaluated at specific time points, -- Memory Content Tracing, viewing the contents of memory as it changed over the simulation, easily going forward and back in time, -- Source code and memory breakpoints in post-processing mode. @Designer also includes all of the features of leading graphical debugging tools, like waveforms, value tracing, source code, schematic and FSM See finite state machine. 1. (mathematics, algorithm, theory) FSM - Finite State Machine. 2. (networking) FSM - FDDI Switching Module. (3Com implements this device on its LAN switches). bubble diagram viewing and waveform compare, which are all inclusive in @Designer version 2.1. The @HDL product family was introduced at the Design Automation Conference in June of this year. "Our customers have found significant value in the @HDL product family, uncovering design problems not previously caught with their existing EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. tools," stated Tarak Parikh, @HDL vice president of Product Engineering. "With this release of @Designer, we are incorporating features which clearly differentiate our product, but more importantly, deliver debugging productivity gains which the Verilog design community has yet to see from the existing products offered in the market." @Designer can also be used in conjunction with the @Verifier automatic formal model checking product, to rapidly debug To correct a problem in hardware or software. Debugging software means locating the errors in the source code (the program logic). Debugging hardware means finding errors in the circuit design (logical circuits) or in the physical interconnections of the circuits. failing properties in the SOC design. @Verifier features automatic property generation and tight integration with Verilog for automatic functional vector generation for use in simulation. Without the need for designers to write properties, @Verifier can automatically detect functional errors, including those caused by synchronization errors between multiple clock domains, deadlocks between interacting state-machines, and RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; code reachability errors. Availability and Limited-time Pricing Promotion @Designer is available for use with Verilog simulators from Cadence, Fintronics, Mentor and Synopsys, running Solaris and Linux operating systems. The software is available for immediate download and evaluation from the company website. In conjunction with the version 2.1 release, @HDL is offering new customers a limited time, special product pricing, available through January 2002. A single quantity, 12-month usage license of @Designer is available for $2,500. Volume pricing is also offered, based on quantity and license time periods. Additionally, all @Designer customers receive a special pricing credit when upgrading to @Verifier. About @HDL @HDL is a privately-held electronic design automation (EDA) company focused on accelerating functional verification of SOCs and silicon IP. The company is pioneering the use of Adaptive Functional Verification (AVF AVF Arteriovenous Fistula AVF All Volunteer Force AVF American Vineyard Foundation AVF Azimuthally Varying Field AVF Ada Validation Facility AVF Augmented Voltage Foot (EKG lead) AVF Average Value Factor ) technology in its @Verifier and @Designer product families. @HDL's products deliver significant verification productivity improvement through SOC system-level design analysis and debugging, automatic formal model checking, and tight integration with existing Verilog simulation environments. For more information, call 408/441-1317, visit www.atHDL.com or email to info@atHDL.com. Note to Editors: @Verifier and @Designer are trademarks of @HDL. All other trademarks are the property of their respective owners. |
|
||||||||||||
Printer friendly
Cite/link
Email
Feedback
Reader Opinion