@HDL Releases Assertion-Based Verification Support for Accellera PSL Sugar Language.Business Editors/High-Tech Writers SAN JOSE San Jose, city, United States San Jose (sănəzā`, săn hōzā`), city (1990 pop. 782,248), seat of Santa Clara co., W central Calif.; founded 1777, inc. 1850. , Calif.--(BUSINESS WIRE)--Jan. 27, 2003 Newest Versions of @HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. Products With Sugar Support to be Demonstrated at Shows in California and Japan; DesignCon and EDS (Electronic Data Systems, Plano, TX, www.eds.com) Founded in 1962 by H. Ross Perot (independent candidate for the President of the U.S. in 1992), EDS is the largest outsourcing and data processing services organization in the country. Fair @HDL, Incorporated, a leading vendor of electronic design automation for accelerating functional verification Functional verification, in electronic design automation, is the task of verifying that the logic design conforms to specification. In everyday terms, functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a complex task, , today announced the release of its @Verifier and @Designer 3.0 products with full support of the Accellera PSL 1. PSL - Portable Standard Lisp. 2. PSL - Problem Statement Language. See PSL/PSA. Sugar 2.0 language. The assertion-based verification and debugging capabilities available in @Verifier and @Designer deliver direct interoperability with the newest release of the Cadence NC-Sim logic simulation Logic simulation is the use of a computer program to simulate the operation of a digital circuit. Logic simulation is the primary tool used for verifying the logical correctness of a hardware design. product, LDV LDV Laser Doppler Velocimetry LDV Light Duty Vehicle LDV Laser Doppler Velocimeter LDV Local Defence Volunteers (Afterwards Home Guard, UK) LDV Limited Dependent Variable LDV Laser Doppler Vibrometers LDV Leyland Daf Vehicles 4.1, which adds simulation support for the PSL Sugar assertion language. @HDL will be demonstrating the @Verifier and @Designer software running with NC-Sim at industry trade shows this week in California at the DesignCon and in Japan at the EDS Fair. "@HDL has implemented support for Sugar 2.0 in its @Verifier and @Designer products within an impressively short time frame. They have done an excellent job in language support and in ensuring tool interoperability. With its comprehensive support of Sugar in both simulation and model checking flows, the @Verifier product will enable design verification teams to immediately incorporate Sugar into their development environments," stated Dr. Yaron Wolfsthal, manager of formal methods at IBM's Haifa, Israel, research lab, where the Sugar language was conceived. "We've run @HDL tools on several multi-million gate ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. designs and have found substantial value in working with our customers to help them filter out problems earlier in the ASIC design cycle," stated Jamshed Qamar, vice president of ASIC Business Development and Engineering, Oki Semiconductor. "We have also started to incorporate the enhanced capabilities of the @HDL tools, which include tighter integration with NC-Sim and automatically extracted assertions in the Sugar format, for IP integration verification." "Assertion-based verification allows chip development teams to eliminate functional errors much earlier in the design process. @HDL has been working closely with Cadence to ensure full interoperability with the newest release of NC-Sim, which incorporates support for Sugar," stated Tarak Parikh, vice president of product engineering for @HDL. "Rapid adoption of assertion-based verification using Sugar will happen as our customers see smooth and effective interoperability between NC-Sim and our @Verifier and @Designer products. We look forward to working co-operatively with Cadence to allow rapid adoption and deployment of Sugar assertion-based verification in the SoC design community." @Verifier 3.0 and @Designer 3.0 With Accellera PSL Sugar Support Both @Verifier 3.0 and @Designer 3.0 are available immediately, running on Linux and Sun/Solaris workstations. Licenses are available for both time-based and perpetual use. @Verifier automatically extracts properties from RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; designs to uncover such problems as multiple clock domain synchronization errors, Finite State Machine See state machine. (mathematics, algorithm, theory) Finite State Machine - (FSM or "Finite State Automaton", "transducer") An abstract machine consisting of a set of states (including the initial state), a set of input events, a set of output events, and a state transition (FSM See finite state machine. 1. (mathematics, algorithm, theory) FSM - Finite State Machine. 2. (networking) FSM - FDDI Switching Module. (3Com implements this device on its LAN switches). ) deadlock, and code reach-ability errors. These automatically extracted properties are also output as Sugar assertions, which can be run directly in NC-Sim simulation, thereby utilizing the existing System-on-Chip (SoC) test benches to uncover other, difficult to find, functional errors. In addition, designers can write their system-level assertions and properties using Sugar 2.0 assertions. These assertions are then run through the formal model checking engines incorporated in @Verifier. The @Verifier-DP product, uniquely offering automatic, distributed processing for model checking, delivers even further productivity gains by running the Sugar assertions on different machines or processors in parallel. The overall model checking run times can therefore be reduced by almost a linear rate. @Designer delivers a next generation graphical debugging and design analysis environment to quickly isolate functional errors during creation, formal model checking, and simulation of Verilog-based designs. Powerful debugging features have been added to allow a unified assertion-based verification and coverage analysis environment for Sugar assertions, with support for analysis of both NC-Sim simulation and @Verifier model checking. Extensive capabilities for debugging RTL, test benches and Sugar assertion coverage and reports are now available for use by design and verification personnel utilizing the Cadence NC-Sim LDV 4.1 simulator. About Accellera PSL / Sugar Accellera is an electronic design automation (EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. ) organization focused on language-based electronic design standards. Accellera's mission is to drive worldwide development and use of standards required by systems, semiconductor and design tools companies, which enhance a language-based design automation process. The Accellera Property Specification Language, PSL, based on the Sugar Assertion language, allows designers to embed information into their designs to facilitate verification. The assertion language enables the design to capture assumptions and partial specifications regarding the operation of a design in a succinct, formal and unambiguous manner. Upcoming Exhibitions @HDL will be demonstrating the @Verifier and @Designer products at two upcoming tradeshows in California and Japan; at the DesignCon 2003, www.designcon.com, Santa Clara Convention Center, California, January 28 and 29, at booth #101, and at the Electronic Design and Solution Fair, www.edsfair.com, Yokohama, Japan, January 30 and 31, at the Innotech booth, #207. About @HDL @HDL is a privately-held electronic design automation (EDA) company focused on accelerating functional verification of SoC and silicon IP designs. The @Verifier and @Designer products deliver significant verification productivity improvement for its customers, including such companies as AMD (Advanced Micro Devices, Inc., Sunnyvale, CA, www.amd.com) A major manufacturer of semiconductor devices including x86-compatible CPUs, embedded processors, flash memories, programmable logic devices and networking chips. , Fujitsu, MegaChips, Oki Semiconductor and Toshiba, through system-level design analysis and debugging, automatic formal model checking, and tight integration with existing Verilog simulation environments. With support of industry standard assertion languages, including OpenVera Assertions (OVA) and the Accellera PSL Sugar language, @HDL enables design teams to reap immediate productivity gains in their System-on-Chip (SoC) verification. @HDL is a member of the Cadence (NYSE NYSE See: New York Stock Exchange :CDN (Content Delivery Network) A system of distributed content on a large intranet or the public Internet in which copies of content are replicated and cached throughout the network. ) Connections Program and the Synopsys (Nasdaq:SNPS SNPS Space Nuclear Power System ) in-Sync Program. For more information, call 408/441-1317, visit www.atHDL.com or email to info@atHDL.com. Note to Editors: @Verifier, @Verifier-DP and @Designer are trademarks of @HDL. All other trademarks or registered trademarks mentioned in this release are the property of their respective owners. |
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