@HDL RELEASES ENHANCED VERSION OF VERILOG DEBUGGING TOOL.

@HDL, Inc. has announced the release of @Designer version 2.1, delivering a new standard of functionality for the graphical debugging and design analysis stages of System-on-Chip (SOC) design. @Designer now supports the leading Verilog simulators, including NC-Verilog and Verilog-XL from Cadence (NYSE:CDN), Modelsim from Mentor Graphics (Nasdaq:MENT), and VCS from Synopsys (Nasdaq:SNPS). SOC design teams can take advantage of the unique capabilities now available in @Designer to significantly improve their verification productivity.

Designer 2.1 includes powerful new features not currently provided in other commercially available products. Designer also includes all of the features of leading graphical debugging tools, like waveforms, value tracing, source code, schematic and FSM bubble diagram viewing and waveform compare, which are all inclusive in @Designer version 2.1.

The @HDL product family was introduced at the Design Automation Conference in June of this year. "Our customers have found significant value in the @HDL product family, uncovering design problems not previously caught with their existing EDA tools," stated Tarak Parikh, @HDL vice president of Product Engineering. "With this release of @Designer, we are incorporating features which clearly differentiate our product, but more importantly, deliver debugging productivity gains which the Verilog design community has yet to see from the existing products offered in the market."

Designer can also be used in conjunction with the @Verifier automatic formal model checking product, to rapidly debug failing properties in the SOC design. @Verifier features automatic property generation and tight integration with Verilog for automatic functional vector generation for use in simulation. Without the need for designers to write properties, @Verifier can automatically detect functional errors, including those caused by synchronization errors between multiple clock domains, deadlocks between interacting state-machines, and RTL code reachability errors.

Designer is available for use with Verilog simulators from Cadence, Fintronics, Mentor and Synopsys, running Solaris and Linux operating systems. The software is available for immediate download and evaluation from the company website. In conjunction with the version 2.1 release, @HDL is offering new customers a limited time, special product pricing, available through January 2002. A single quantity, 12-month usage license of @Designer is available for $2,500. Volume pricing is also offered, based on quantity and license time periods. Additionally, all @Designer customers receive a special pricing credit when upgrading to @Verifier.

@HDL is a privately-held electronic design automation (EDA) company focused on accelerating functional verification of SOCs and silicon IP. The company is pioneering the use of Adaptive Functional Verification (AVF) technology in its @Verifier and @Designer product families. @HDL's products deliver significant verification productivity improvement through SOC system-level design analysis and debugging, automatic formal model checking, and tight integration with existing Verilog simulation environments.