@HDL Launches Web-based Seminar Series; Company to Offer Web-Cast Interactive Sessions on Accelerating Functional Verification of SoC Designs.

Business Editors/High-Tech Writers

SAN JOSE, Calif.--(BUSINESS WIRE)--July 26, 2002

@HDL, an emerging leader in design automation for accelerating functional verification, is announcing the launch of Web-based seminars for designers of System-on-Chip (SoC) circuits. Three seminars are available to the design community, which will be hosted by Tarak Parikh, @HDL Vice President of Product Engineering. Registration for the WebEx based seminars can be made through the company Web site, www.atHDL.com, with the first seminar beginning Tuesday, July 30. The three seminars include:

-- Unifying Assertion-based Functional Verification Due to an overwhelming response from the seminars at DAC, @HDL will be offering an online version of this seminar. The seminar presents the significant benefits of a unified simulation and formal model checking based functional verification methodology.

-- Next-Generation Graphical Debugging of Simulation, Model Checking, and Test-benches

-- Multiple Clock Domain Analysis and Verification

About @HDL

@HDL is a privately held electronic design automation (EDA) company focused on accelerating functional verification of SoC and silicon IP designs. The @Verifier and @Designer products deliver significant verification productivity improvement for its customers, including such companies as AMD, OKI Semiconductor, and Toshiba, through system-level design analysis and debugging, automatic formal model checking, and tight integration with existing Verilog simulation environments. With support of industry standard assertion languages, including OpenVera Assertions and Accellera Sugar language, @HDL enables design teams to reap immediate productivity gains in their System-on-Chip (SoC) verification. For more information, call [phone], visit www.atHDL.com or email to [e-mail].