@HDL Appoints Innotech as Its Japanese Distributor.Business Editors/High-Tech Writers SAN JOSE San Jose, city, United States San Jose (sănəzā`, săn hōzā`), city (1990 pop. 782,248), seat of Santa Clara co., W central Calif.; founded 1777, inc. 1850. , Calif.--(BUSINESS WIRE)--Oct. 15, 2001 Sales and Support Agreement Brings New Generation of Functional Verification Software to SOC/ASIC Design Community @HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. , Inc. today announced an agreement with Innotech Corporation, based in Japan, to distribute and support the newly introduced @HDL family of functional verification Functional verification, in electronic design automation, is the task of verifying that the logic design conforms to specification. In everyday terms, functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a complex task, software, @Verifier(TM) and @Designer(TM). The agreement between the two companies covers all aspects of marketing, pre-sales, and on-going technical support, and is aimed at addressing the needs of Japanese SOC/ASIC engineers looking to break through the bottlenecks in design verification. The @Verifier and @Designer products were introduced at the Design Automation Conference in June of this year. Since their release, customers in North America North America, third largest continent (1990 est. pop. 365,000,000), c.9,400,000 sq mi (24,346,000 sq km), the northern of the two continents of the Western Hemisphere. have found significant value in the @HDL product family, uncovering design problems not previously caught with their existing EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. tools. "The most important challenge for our customers is to find ways to significantly improve engineering productivity," stated Yasuhiko Nishikubo, managing director of the Design Systems Division of Innotech. "The historical bottlenecks in functional verification require new methods and products. Innotech is confident that the @HDL products will deliver significant benefits in rapidly identifying and isolating design errors much earlier in the SOC development schedule." "With the wealth of technical expertise and market reach to the leading-edge companies in Japan, Innotech provides @HDL with a world-class business development partner," stated Badru Agarwala, president, CEO (1) (Chief Executive Officer) The highest individual in command of an organization. Typically the president of the company, the CEO reports to the Chairman of the Board. and co-founder of @HDL. "We are looking forward to working with Japanese SOC design teams searching to significantly raise their functional verification productivity, and we have great confidence in Innotech to provide the expert service and support required." About @Verifier and @Designer @Verifier incorporates Adaptive Functional Verification to detect the toughest bugs by providing a hybrid solution that automatically combines the benefits of formal model checking and intelligent-random simulation techniques. The tool features automatic property generation and tight integration with Verilog for intelligent-random simulation. Without the need for designers to write properties, @Verifier can automatically detect functional errors, including those caused by synchronization errors between multiple clock domains, deadlocks between interacting state-machines, and RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; code reachability errrors. @Verifier complements other commercial testbench environments and methods including those that involve Verisity's (Nasdaq:VRST VRST Virtual Reality Software and Technology VRST Virtual Reality System Testing ) Specman Elite(TM) and Synopsys' (Nasdaq:SNPS SNPS Space Nuclear Power System ) Vera(TM). The @Designer product raises the level of debugging abstraction to the transaction and protocol level, allowing the user to debug To correct a problem in hardware or software. Debugging software means locating the errors in the source code (the program logic). Debugging hardware means finding errors in the circuit design (logical circuits) or in the physical interconnections of the circuits. at the system-level, while the design works at the signal level. The tool provides a wide array of analysis and debugging features that make it the new standard in graphical user interfaces graphical user interface (GUI) Computer display format that allows the user to select commands, call up files, start programs, and do other routine tasks by using a mouse to point to pictorial symbols (icons) or lists of menu choices on the screen as opposed to having to for IP block and SOC verification. Upcoming Exhibitions and Seminars Innotech and @HDL will host a technical seminar in Japan, scheduled for October 30, 2001 at the Innotech offices in Shin-Yokohama. @HDL will also be participating at the EDA Front-to-Back Conference, scheduled for November 14-15, 2001, at the San Jose Convention Center, in California. About Innotech Innotech was founded in 1987 as a distributor of semiconductor manufacturing equipment, EDA tools and semiconductor products with the corporate principle to provide customers with high value-added products and services, and contribute to the development of the semiconductor industry in Japan. Innotech is headquartered at 3-17-6, Shinyokohama, Kouhoku-ku, Yokohama-shi, Kanagawa, 222-8580 Japan. For more information call 81-45-474-9000, or visit at www.innotech.co.jp About @HDL @HDL is a privately-held electronic design automation (EDA) company focused on accelerating functional verification of SOCs and silicon IP. The company is pioneering the use of Adaptive Functional Verification (AVF AVF Arteriovenous Fistula AVF All Volunteer Force AVF American Vineyard Foundation AVF Azimuthally Varying Field AVF Ada Validation Facility AVF Augmented Voltage Foot (EKG lead) AVF Average Value Factor ) technology in its @Verifier and @Designer product families. @HDL's products deliver significant verification productivity improvement through SOC system-level design analysis and debugging, automatic formal model checking, and tight integration with existing Verilog simulation environments. For more information, call 408/441-1317 or visit www.atHDL.com. Note to Editors: @Verifier and @Designer are trademarks of @HDL. All other trademarks are the property of their respective owners. |
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