@HDL Announces Support for OpenVera Assertions; Functional Verification Product Family to Incorporate Assertions Developed by Synopsys and Intel.Business Editors/High-Tech Writers Design Automation Conference 2002 SAN JOSE San Jose, city, United States San Jose (sănəzā`, săn hōzā`), city (1990 pop. 782,248), seat of Santa Clara co., W central Calif.; founded 1777, inc. 1850. , Calif.--(BUSINESS WIRE)--April 15, 2002 @HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. , Inc. today announced plans to enhance its family of functional verification Functional verification, in electronic design automation, is the task of verifying that the logic design conforms to specification. In everyday terms, functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a complex task, products to support the OpenVera(TM) assertion language, jointly developed by Synopsys (Nasdaq:SNPS SNPS Space Nuclear Power System ) and Intel. @HDL will be developing a bi-directional interface to support assertion-based design flows. The bi-directional interface will deliver the powerful capabilities of the @Verifier and @Designer products from @HDL to the emerging OpenVera assertions community for the verification of system-on-chip (SoC) designs. Initial @HDL product support for OpenVera assertions is scheduled for June 2002. "Our customers are looking for Looking for In the context of general equities, this describing a buy interest in which a dealer is asked to offer stock, often involving a capital commitment. Antithesis of in touch with. an effective support of their assertion-based methodology, allowing for integrated tools that can take advantage of both formal model checking and simulation," stated Tarak Parikh, @HDL vice president of product engineering. "Our @Verifier product supports extensive automatic property extraction and powerful formal model checking technology to improve the productivity of design and verification teams. We will automatically generate OpenVera assertions for these properties, covering such design errors as clock domain synchronization, finite-state machine errors, multi-cycle and false path problems." "OpenVera 2.0 with new assertions combines the strengths of the OpenVera hardware verification language A Hardware Verification Language, or HVL, is a programming language used to verify the designs of electronic circuits written in a hardware description language. HVLs typically include features of a high-level programming language like C++ or Java as well as features for and Intel's newest formal verification
In the context of hardware and software systems, formal verification language, ForSpec," stated James Watts James Watts may refer to:
Availability @HDL is committed to support the evolving standardization efforts in the area of assertion-based methods. With support of the OpenVera assertion language, @HDL will enable design teams to reap immediate productivity gains in their SoC functional verification. Versions of @Verifier and @Designer will be offered by @HDL, which include a bi-directional interface with OpenVera design flows. Product packaging and customer availability information will be announced at the upcoming Design Automation Conference (DAC See D/A converter and discretionary access control. DAC - Digital to Analog Converter ), scheduled for June 2002. Customers interested in evaluating the integrated @Verifier / OpenVera flow should contact the company directly, or request further information from the company website, www.atHDL.com. About OpenVera OpenVera is an open source hardware verification language developed specifically to meet the unique requirements of functional verification. The language enables users to describe the target application environment, including complex protocols and data objects, at a high level of abstraction The level of complexity by which a system is viewed. The higher the level, the less detail. The lower the level, the more detail. The highest level of abstraction is the single system itself. , which dramatically increases productivity, readability and reusability. For more information on OpenVera, visit www.open-vera.com. About @HDL @HDL is a privately-held electronic design automation (EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. ) company focused on accelerating functional verification of SOCs and silicon IP. The @Verifier and @Designer products deliver significant verification productivity improvement through system-level design analysis and debugging, automatic formal model checking, and tight integration with existing Verilog simulation environments. For more information, call 408/441-1317, visit www.atHDL.com or email to info@atHDL.com. Note to Editors: @Verifier and @Designer are trademarks of @HDL. Synopsys is a registered trademark of Synopsys, Inc. OpenVera is a trademark of Synopsys, Inc. All other trademarks or registered trademarks mentioned it this release are the property of their respective owners. |
|
||||||||||||||||
Printer friendly
Cite/link
Email
Feedback
Reader Opinion