@HDL Announces Special Presentations at Design Automation Conference; Synopsys and Verification Central to Participate in @HDL Assertion-Based Functional Verification Seminar.Business Editors/High-Tech Writers Design Automation Conference 2002 SAN JOSE San Jose, city, United States San Jose (sănəzā`, săn hōzā`), city (1990 pop. 782,248), seat of Santa Clara co., W central Calif.; founded 1777, inc. 1850. , Calif.--(BUSINESS WIRE)--May 28, 2002 @HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. , Inc., an emerging leader in design automation for accelerating functional verification Functional verification, in electronic design automation, is the task of verifying that the logic design conforms to specification. In everyday terms, functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a complex task, , today announced plans to hold special presentations during the upcoming Design Automation Conference (DAC See D/A converter and discretionary access control. DAC - Digital to Analog Converter ) in New Orleans New Orleans (ôr`lēənz –lənz, ôrlēnz`), city (2006 pop. 187,525), coextensive with Orleans parish, SE La., between the Mississippi River and Lake Pontchartrain, 107 mi (172 km) by water from the river mouth; founded . Synopsys, Inc., Verification Central and @HDL will be participating in the presentation, entitled "Unifying Assertion-Based Verification." The speakers will highlight the significant productivity benefits derived from a unified simulation and formal model checking-based functional verification methodology. Key to this unification is an assertion-based flow that has been incorporated in the family of products from @HDL, including support for the OpenVera(TM) assertion language. The presentation will be held twice a day during the DAC conference, Monday, Tuesday and Wednesday, June 10-12, at the @HDL Demo Suite, No. 3652, beginning at 11:00 am and at 3:00 pm, and will run for 45-minutes. Attendance at the presentation is by advanced registration at the @HDL website, www.atHDL.com. @HDL is committed to supporting the evolving standardization efforts in the area of assertion-based functional verification. With support of industry standard assertion languages, @HDL will enable design teams to reap immediate productivity gains in their System-on-Chip (SoC) verification. @HDL product demonstrations will be offered at DAC which include bi-directional interfaces with standard assertion language design flows. About @HDL @HDL is a privately-held electronic design automation (EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. ) company focused on accelerating functional verification of SoC and silicon IP designs. The @Verifier and @Designer products deliver significant verification productivity improvement for it's customers, including AMD (Advanced Micro Devices, Inc., Sunnyvale, CA, www.amd.com) A major manufacturer of semiconductor devices including x86-compatible CPUs, embedded processors, flash memories, programmable logic devices and networking chips. and OKI Semiconductor, through system-level design analysis and debugging, automatic formal model checking, and tight integration with existing Verilog simulation environments. For more information, call 408/441-1317, visit www.atHDL.com or email to info@atHDL.com. Note to Editors: @Verifier and @Designer are trademarks of @HDL. Synopsys is a registered trademark of Synopsys, Inc. OpenVera is a trademark of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the property of their respective owners. |
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