60 Tapeouts: Kawasaki Standardizes On Sequence for ''Most Accurate'' Signal-Integrity Signoff; Global ASIC Player Eliminates SI Defects.

Business Editors/High-Tech Writers

SANTA CLARA, Calif.--(BUSINESS WIRE)--Nov. 6, 2002

To achieve rapid design closure and consistent quality in its sub-180 nanometer ASICs, Japan's Kawasaki Microelectronics, Inc., and Kawasaki LSI have made Sequence Design's PhysicalStudio(TM) SI signoff solution part of its standard design flow worldwide. Kawasaki's ASIC Business Unit produces a range of ICs for applications including multimedia, networking, communications, and personal computing.

"We have taped out over 60 designs using PhysicalStudio's signal-integrity signoff capability," said Yoshito Muraishi, deputy general manager, Kawasaki Microelectronics, Product Development and Design Department. "We have received silicon for all of these designs and have not seen any signal-integrity issues in them. This clearly demonstrates that the product was able to detect all the problems before tapeout, saving us several silicon respins. We are extremely happy with PhysicalStudio and have made it an integral part of our signoff flow for all 0.13u and 0.18u designs."

An added advantage in adopting Sequence's SI solution was its "simple and seamless" integration with Kawasaki's existing Cadence flow, Mr. Muraishi noted.

"There have been no crosstalk problems in the actual silicon since we adopted the Sequence tools," Mr. Muraishi said.

"We are extremely proud of the fact that all of these tapeouts have resulted in silicon free of signal-integrity defects," Sequence senior vice president of R&D and product marketing, Susheel Chandra, said. "As our customers continue to push the limits of IC technology, Sequence will remain their steadfast ally in nanoscale design and manufacturing."

Concurrent View Needed

There are four major SoC design-closure issues: timing, signal integrity, power, and clock. All are interdependent, necessitating a concurrent view to resolve them. Resolving them calls for a blend of extraction, timing analysis, signal-integrity analysis, and optimization in a single engine. Failure to account for these effects concurrently inevitably leads to diminished performance and increased time to market.

PhysicalStudio optimizes chip timing and signal-integrity issues concurrently, both before and after routing. It is fully interoperable with industry-standard routing tools, permitting existing physical design flows to reach fast, predictable design closure in silicon geometries below 180 nanometers.

About PhysicalStudio

PhysicalStudio allows system-on-chip designers to:

-- reach 35% higher clock speeds

-- achieve a 5-15% reduction in power over traditional physical design flows

-- compensate for signal integrity effects, such as crosstalk-induced "setup" violations and "hold" violations and functional "glitch" errors

-- accurately predict and immunize against noise during placement

-- surgically correct timing and signal-integrity issues "along the route" using a patent-pending FullContext post-route technique

By unifying placement-driven optimization and post-route optimization into a single engine, the product ensures that every net in a design is correctly driven and all timing and signal integrity violations are eliminated. PhysicalStudio operates on large, hierarchical designs with varying abstractions at the top-level such as register-bounded blocks, STAMP, LIB and CLF.

About Kawasaki Microelectronics

Kawasaki Microelectronics, Inc. is an LSI (Large Scale Integrated Circuits) design and manufacturing company, established as the LSI Division of Kawasaki Steel Corporation (KSC) in 1990 and spun off from KSC as an independent entity on July 1, 2001. For more information: http://www.k-micro.com/english.html.

Kawasaki Microelectronics has developed unique ASICs for communication equipment, PC peripherals, and other electronic products for both U.S. and Japanese markets. Kawasaki Microelectronics maintains an advanced Electronics Center in Chiba, Japan. The company's North American subsidiary, Kawasaki LSI U.S.A., Inc., has engineering and sales offices in San Jose, Calif., and Boston, Mass. For more information: http://www.klsi.com/.

About Sequence

Sequence Design, Inc., the SoC Design Closure Company(SM), enables system-on-chip designers to bring higher-performance and lower-power integrated circuits quickly to fabrication. Sequence's physical design software and solutions give its more than 100 customers the competitive advantage they need to excel in aggressive technology markets, despite demanding complexity and time-to-market issues of sub-180 nanometer designs.

Sequence has worldwide development and field service operations. The company was recently named by Reed Electronics as one of the top 50 companies to watch in the electronics industry. Sequence is privately held. Sequence is a member of Cadence Design Systems' Connections(TM) and Mentor Graphics' Open Door(TM) partnership programs. Additional information is available at sequencedesign.com.

Note to Editors: All trademarks mentioned herein are the property of their respective owners.