5-V MCU Support IC Has 2,500 Gate CPLD, EPROM & SRAM; Draws 96% Less Power.

FREMONT, Calif.--(BUSINESS WIRE)--May 4, 1998--WSI, Inc. today introduced a highly integrated, 5-volt, zero-power MCU peripheral IC that consumes only 0.8 mA/MHz when operating and 5 microamps in standby.

The ZPSD6XX integrates 2,500 gates of Micro-Cell(TM) programmable logic with 128 Kbytes of EPROM, 512 bytes of SRAM, extra I/O and a programmable MCU interface.

"The ZPSD6XX provides the world's lowest power means of adding program store and programmable logic to embedded system designs," said David Raun, WSI's vice president of PSD product marketing. "In a typical MCU-based system, operating at an MCU clock frequency of 16 MHz, the ZPSD6XX draws only 6.2 mA fully loaded. That's about 40% less operating power than the 10 mA consumed by a stand-alone EPROM and 96% less power than a discrete solution that includes the logic, address decoding, SRAM and I/O.

"Forty-percent of embedded system designers use programmable logic to design peripherals, such as serial channels or mail boxes," Raun explained. "A substantial proportion of that logic is required just to connect the MCU address/data bus to the PLD flip-flops. Additional logic is needed to decode addresses. In fact, this "interface" logic often represents a larger portion of the CPLD resources than the peripheral. As a result, designers end up using a larger CPLD than is actually required for the peripheral alone. Since PLD power consumption is a direct function of the number of product terms used, the need to build the interface to the MCU ratchets up the system power drain. For example, a 7032 used to implement a serial channel draws more than 70 mA in a system with a 16 MHz clock," Raun explained.

"The Micro-Cell CPLD on the 5-volt ZPSD6XX radically reduces the number of product terms used to implement a peripheral by providing an extra bus that connects each and every flip-flop directly to the MCU address data bus. The ZPSD6XX flip-flops can be decoded and written to without using any product terms or macrocells. The ZPSD6XX also has a built-in address decoder and MCU interface. Altogether, the Micro-Cell architecture saves the equivalent of about 1,200 logic gates and a disproportionate amount of power consumption. Thanks to WSI's zero-power architecture, the ZPSD6XX can implement the serial channel described above in just 12 Micro-Cells, consuming only 6.2 mA including the EPROM, SRAM and extra I/O integrated on the chip. That is about 92% less power consumption that the 7032 in the same application.

"But this isn't just a low power story," Raun continued. "The design cycle in shortened by several weeks because engineers don't have to design and debug all that glue, decode and interface logic that would be required to connect a conventional PLD and memory to a microcontroller."

Low Power Operation Enabled By WSI's Zero-power Technology

WSI's patented zero-power chip architecture enables the ultra-low power consumption of the ZPSD6XX. Address transition detection (ATD) circuitry prevents the chip from being powered up unless an input signal changes. In addition, WSI's Alternate Partitioned Metal Virtual Ground (AMG) NVM architecture, dual pass transistor logic (DPTL), and differential methods of signal sensing reduce the signal swing, capacitance and the time required to read the signal.

Cuts Several Weeks From The Product Development Cycle

By eliminating the need to generate complex logic equations for the MCU's chip select, read and write signals, and address and data busses, the Micro-Cell PLD architecture can cut several weeks from the product development cycle. ZPSD6XX devices also provide a programmable MCU interface that can be configured in a few minutes to work with any MCU from Intel, Motorola, Philips or others. Designing and debugging an MCU interface with port extenders, counters, or EPROM can require as long as two weeks. Any change in the bus frequency, bus width or MCU type will require a new interface design. By providing direct MCU communication in the device architecture, ZPSD6XX devices eliminate this extra design time.

Communicating with Microcontrollers

All MCUs require address bus, data bus, chip select, and read or write signals to communicate with microperipherals implemented in programmable logic. In addition, the chip select and the microperipherals in the PLD must reside in the address space of the MCU and must be decoded. Any system that is using conventional programmable logic to connect multiple MCUs to each other or to connect an MCU to an external device, such as a sensor, face several drawbacks that are eliminated by the ZPSD6XX Micro-Cell programmable logic.

Windows-based Tools Ensure Efficient Silicon Utilization

WSI provides PSDsoft design tools that eliminate the need for the designer to understand or manipulate the architecture of the ZPSD6XX. The designer need only enter the logic design using any combination of Data I/O's AHDL hardware description language, logic equations, boolean equations, truth tables, or state diagrams. A decompiler allows previous PSD designs to be uploaded, decompiled and modified. Many AHDL designs that have been implemented in another type of EPLD may be copied into PSDsoft and migrated to the programmable logic on the ZPSD6XX with minimal modification. PSDsoft automatically and transparently optimizes the logic so that flip-flop configuration, product term allocation between Micro-Cells, and Micro-Cell allocation to I/O pins result in the most efficient utilization of the silicon. PSDsoft then maps the MCU code and the logic into the ZPSD6XX, ensuring that there is no overlapping of address locations. Absolutely no user-intervention is required. PSDsoft uses Data I/O's ABEL for logic design and Simucad's SILOS III Verilog simulator for full-chip simulation.

Pricing, Packaging, and Availability

Production quantities of ZPSD6XX MCU support ICs are available now and are priced as low as $4.97 in quantities of 10,000. ZPSD6XX devices are available in 52 pin ceramic and plastic leaded chip carrier packages. The PSDsoft Lite design tool suite is available now for $99.

WSI is the leading supplier of highly integrated, programmable solutions for high-speed embedded control designs. Its PSD families of single-chip, field-programmable microcontroller peripherals off-load microcontroller functions so that MCUs can operate faster and do more. The power-conserving features of PSD devices can extend system battery life by several hours. The company's family of high performance non-volatile memory products offers densities of 16 Kbit to 1 Megabit with access times as low as 25 ns and 3.3 volt devices with access times as low as 70 ns. WSI is located in Fremont. -0-

Note to Editors: PSDsoft is a trademark of WSI. Magic PRO III is a registered trademark of WSI. Windows and Windows 95 are registered trademarks of Microsoft Corporation. ABEL is a registered trademark of DATA I/O. Silos III is a trademark of Simucad.

(1) A typical 8- or 16-bit MCU, such as a 68HC11 or 80196, running with a 16 MHz clock frequency, will result in a 4 MHz bus. Power drain for the ZPSD6XX and competitive alternatives are based on a 4 MHz bus. This is the equivalent of a 16 MHz MCU clock in these types of systems.

CONTACT: WSI

Dale Prull, 510/498-1723

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The William Baldwin Group

Nancy B. Green, 650/856-6192

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