2.7 V MCU Support IC With CPLD and Memory Cuts Power Drain by 97%.

FREMONT, Calif.--(BUSINESS WIRE)--Sept. 22, 1998--WSI, Inc. today introduced the 2.7-volt ZPSD6XXV, the world's lowest power means of adding logic or program store to MCU-based designs.

Ideal for portable, battery operated systems, this MCU peripheral IC integrates a 2,500 gate CPLD, 128 Kbytes of EPROM, 512 Bytes of SRAM, extra I/O, and a programmable interface to most 8- or 16-bit MCUs. However, this ultra-low power device consumes 97% less power than a discrete solution with comparable functionality.

In a system operating at 1 MHz, the ZPSD6XXV consumes only 0.76 mA, including I/O loading. This is 97% less power drain than the 25.1 mA consumed by a 3 volt solution that includes the same memory and logic densities and I/O. In standby, the ZPSD6XXV consumes just 1 microamp, 99% less than the discrete solution.

WSI's vice president of PSD product marketing, David Raun, said of the new device, "Nearly half of embedded system designers use programmable logic to design peripherals such as serial channels or mail boxes. Unfortunately these CPLDs consume a lot of power. In a system operating at just one megahertz, Altera's (Nasdaq:ALTR) 3-volt EPF7032LV will add about 15 mA of power drain. When you consider that a typical 3-volt 68HC11 draws only 4 mA, that is a tremendous increase in power consumption," Raun explained.

"If the program code has outgrown the 4-Kbytes of memory on the typical single-chip MCU, the designer is also going to need an external EPROM as well. That will add another 4.5 mA to system power drain. So all of a sudden, the microcontroller, the CPLD, external program store and associated latches and I/O will add about 25 mA to system power drain -- this is five times more than the single-chip MCU! In a power-constrained system, this may be unacceptable. These extra chips are also going to increase board real estate substantially," Raun explained.

"WSI's new ZPSD6XXV provides all the above functionality to these types of designs, while drawing only 0.76 mA. That's pretty impressive," Raun concluded. CPLD Logic Architecture Developed Specifically For Use with MCUs

WSI has implemented the CPLD on the ZPSD6XXV using the company's recently introduced Micro-Cell(tm) logic architecture. Much like other sophisticated CPLDs, the ZPSD6XXV has both input and output macrocells, plus product term and macrocell allocators. Unlike conventional CPLDs, however, the Micro-Cell CPLD has been developed specifically for use with microcontrollers.

It has an extra address/data bus that gives the MCU direct access to the micro-cell flip-flops, thereby allowing the MCU to write directly to or read directly from the input or output micro-cell flip-flops without going through the PLD array. This ability of the MCU to communicate directly with the flip-flops means that valuable preset, clear, OR, and clock product terms can be saved for the implementation of peripheral logic, instead of being used to connect the MCU to macrocell flip-flops.

As many as 32 products terms, representing approximately 1,200 logic gates are freed up by the Micro-Cell architecture. Since power consumption is a direct function of the number of product terms used, the Micro-Cell architecture significantly contributes to the low power drain of the ZPSD6XXV.

Since the ZPSD6XXV flip-flops can be decoded and written to without using any product terms or macrocells, the ZPSD6XXV is ideal for dual-processor applications such as serial channels or mail boxes. This direct MCU connection significantly reduces the amount of time required to write firmware. WSI's Zero-Power Technology Allows Lowest Power Consumption In the World

The ZPSD6XXV's low power drain is the result of WSI's patented zero-power chip architecture. Address transition detection (ATD) circuitry on the chip prevents any portion of it from being powered up unless an input signal changes. In addition, WSI's Alternate Partitioned Metal Virtual Ground (AMG) NVM architecture, dual pass transistor logic (DPTL), and differential methods of signal sensing radically reduce signal swing, capacitance and the time necessary to read the signal. Product Development Time Cut By Several Weeks

A single chip MCU with external EPROM or logic will require an MCU interface and port extenders that can take as long as two weeks to design and debug. Any changes in the bus frequency, bus width or MCU type will require a new interface design. The ZPSD6XXV cuts the design cycle by supplying a built-in programmable MCU interface. The Micro-Cell PLD architecture eliminates the need to generate complex logic equations for the MCU's chip select, read and write signals, and address and data busses. Logic Resources

The ZPSD6XXV has 26 configurable I/O ports, 23-input Micro-Cells and 12 output Micro-Cells -- sufficient logic to implement key pad encoders, stepper motor control, a dual processor interface, bus interfaces, waveform generation, frequency dividers, counters, serial channels, system chip select generation and wait state generation. Silicon Efficiency Guaranteed with Windows-Based Tools

WSI's PSDsoft design tools automatically and transparently optimize the logic so that flip-flop configuration, product term allocation between Micro-cells, and Micro-Cell allocation to the I/O pins result in the most efficient utilization of the silicon. The MCU code and the logic are then mapped into the ZPSD6XXV by PSDsoft to ensure no overlap of address locations. User intervention is unnecessary.

Logic designs may be entered using any combination of Data I/O's AHDL hardware description language, logic equations, boolean equations, truth tables, or state diagrams. PSD designs can be uploaded, decompiled and modified using PSDsoft's decompiler. With only slight modification, most AHDL designs that have been implemented in other EPLD architectures, such as the EPM7032, can be migrated to the programmable logic on the ZPSD6XXV. PSDsoft uses Data I/O's ABEL for logic design and Simucad's SILOS III Verilog simulator for full-chip simulation. Pricing, Packaging and Availability

ZPSD6XXV MCU support ICs are available now in 52 pin ceramic and plastic leaded chip carrier packages. Prices start at $5.15 (ZPSD611E1V-25J) in quantities of 10,000. The PSDsoft Lite design tool suite is available now for $99.

WSI is the leading supplier of highly integrated, programmable solutions for high-speed embedded control designs. Its PSD families of single-chip, field-programmable microcontroller peripherals off-load microcontroller functions so that MCUs can operate faster and do more. The power-conserving features of PSD devices can extend system battery life by several hours. The company's family of high performance non-volatile memory products offers densities of 16 Kbit to 1 Megabit with access times as low as 25 ns and 3.3 volt devices with access times as low as 70 ns. WSI is located in Fremont.

Note to Editors: PSDsoft is a trademark of WSI. Magic PRO III is a registered trademark of WSI. Windows and Windows 95 are registered trademarks of Microsoft Corporation. ABEL is a registered trademark of DATA I/O. Silos III is a trademark of Simucad.