0.25mm system-level ASIC family from Toshiba integrates more than 10M usable gates; unified cell array architecture lets designers mix and match gate array cells or standard cells on same die.

SAN JOSE, Calif.--(BUSINESS WIRE)--May 29, 1997--Toshiba America Electronic Components, Inc. (TAEC) today announced a new family of 0.25 micron (mm) drawn system-level ASICs integrating more than 10 million usable gates at 42 picoseconds (ps). The TC240 is based on a new Unified Cell Array Architecture that provides designers with the flexibility of combining gate array cells, standard cells and custom blocks on the same die to achieve performance, functionality, cost and time-to-market design goals.

"The old chip implementation methodologies of gate array, embedded array and standard cell run out of steam as megagate system-level ASIC complexity explodes," stated Larry Jordan, senior vice president and general manager at TAEC's San Jose, Calif.-based System IC Division (SID). "Hence, we developed the Unified Cell Array Architecture for our 0.25mm generation ASICs which uses a common routing grid structure and basic cell architecture allowing designers to mix and match gate array or standard cells as well as power or performance optimized cells on a single die. Using this approach, system designers can optimize each function of the chip and balance performance, power, cost and time-to-market requirements."

The TC240 is targeted at high density applications including personal computers, networking, advanced graphics and set-top boxes.

The TC240 employs shallow trench isolation and a five layer, no overlap, stacked via metal process to achieve 35K gates per square millimeter gate density, or more than 10 million usable gates on a die, more than three times greater than the previous 0.3mm TC220 ASIC. Propagation delay of a 2-input NAND gate is 42ps, which is a 30 percent performance improvement compared to TC220. Up to four metal layers are used for interconnects while the fifth layer provides a bonding pad array for high pin count flip chip designs.

TC240 is compatible with Toshiba's dRAMASIC(tm) families. The TC230D and TC240D 1T dRAMASIC families, announced last month, integrate up to 128 megabit (Mb) embedded DRAM and over 400K usable gates.

TC240 uses a 2.5 volt (V) power supply for the core logic; power consumption of a low-power 2-input NAND gate is as low as 0.06 microwatt (mW)/MHz. To maintain a simple interface with existing peripheral devices, the I/O power supply is 3.3V. For very low power requirements, the internal power supply can be lowered to 1.8V, cutting power consumption by almost half.

A wide variety of system cores, functional blocks, I/O cells and memories are available. The system cores are consistent with the Virtual Socket Interface Alliance principles. These system elements include: -0-

--  RISC microprocessor cores and peripherals based on the MIPS RISC
     architecture
--  CISC microprocessor cores and peripherals
--  Multimedia
--  Networking
--  Memories including dRAMASIC cells
--  High-speed I/Os

TC240, like all of Toshiba's ASIC products, is fully supported by standard commercial EDA tools.

Available packages include high pin count high performance flip chip BGA, low cost TBGA and TAB-FP packages and CSPs for minimum assembly space. Toshiba is actively soliciting design-ins and making production commitments. Production is scheduled for second quarter, 1998. Customers should contact their nearest Toshiba sales office for pricing details. Pricing depends on product complexity and packaging.

TAEC is the North American manufacturing, sales and marketing arm of one of the world's largest suppliers of semiconductors, integrated circuits and electronic components for industrial and consumer applications. The company is the recognized leader in CMOS technology and has one of the broadest IC product lines in the industry. In addition, Toshiba is a leading manufacturer of technologically advanced electron tubes and solid state devices, including color picture tubes, display monitor tubes, liquid crystal displays, medical tubes, rechargeable batteries, microwave components, laser diodes and optical transmission devices.

The Systems IC Division is located at 1060 Rincon Circle, San Jose, CA 95131. For more company information, please visit TAEC's Internet home page at: http://www.toshiba.com/taec . -0-

Editors Note: Reader inquiries please publish [phone]. dRAMASIC is a trademark of Toshiba Corporation.

CONTACT: Toshiba America Electronic Components Inc.

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or

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