0.1 cent RFID chip assembly? Technologies to slash manufacturing costs for the ubiquitous tags are being aggressively pursued.

Ed.: For the full article, please see circuitsassembly.com/cms/content/view/2291/

RFID applications are boundless. Technical analysis shows that broad-based applications of RFID will develop in two distinct phases. Phase 1, currently underway, is showing only marginal advances because RFID is superficially tacked onto existing business processes. The revolution will come during Phase 2: radical process reengineering and new RFID-centered business models. This phase will relaunch RFID as a new base technology. In addition, analysts say industry executives are focusing only on the price of RFID tags and when they will drop. Instead, industry should dedicate more creative resources to advancing manufacturing technologies.

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Nevertheless, price is the significant benchmark for RFID tags to be accepted in broad markets. There is talk of the nickel tag, a fully functional passive RFID transponder for just a 5 cents per unit, which will be available by 2008. In 2003, the average price point of RFID tags was ten times this value. But now evidence of a new wave of technology enablers will drive down the production cost of RFID tags. This article looks at the cost of chip assembly and the various ways it can be implemented.

The method of assembling a chip onto a substrate (conventional die bonding technology) has been developed and optimized for decades. Based on this know-how, equipment vendors developed advanced die bonder for high-speed flip-chip assembly. Due to the huge demand predicted for RFID tags, a couple of visionary alternative approaches--for example, Fluidic Self Assembly (1) and Vibratory Assembly (2) --seem to offer a solution (Figure 1).

The big advantages of conventional and advanced die bonders are their mature technology, low investment risk and high-yield operation. For the assembly of high-end flip-chip devices like DSPs and ASICs, an assembly yield of >99.95% is a standard target. For low-end flip-chip devices like RFID tags, a yield of 98% is standard, with 99% yield realistic provided all process and material parameters are well controlled, and 99.5% reachable in the mid-term timeframe.

This simple calculation helps explain the cost pareto of yield loss. A complete chip assembly line including adhesive application, flip-chip attach, curing, testing and slitting is currently available at a market price of <$1 million. With 7,400 hours of productive time, a line throughput of 10,000 UPH, and five years' depreciation, the costs of chip assembly are 0.27 cents per tag. Assume a further 15 cents for the cost of an RFID tag and consider a yield loss of 2%. This calculates to a cost of yield loss of 0.3 cents, which exceeds the depreciation costs of the equipment. This example illustrates the high value of mature high-yield assembly equipment.

Direct and Indirect Chip Assembly

In the manufacturing of RFID tags, a basic distinction exists between direct chip assembly and indirect chip assembly (Figure 2). In direct assembly, the chip's bumps are positioned and placed directly onto the antenna connections by means of flip-chip technology. The key advantage is a lower packaging cost, because this requires fewer process steps and consumes less material. However, despite the large antenna pitch, high throughput rates necessitate negligible indexing timing. Thus, with a conventional flip-chip bonder approach, the technology is not without its challenges. The bigger the bonding area of the antenna web, the more manageable those challenges are. However, the tradeoff with a bigger bonding area is a longer travel time for chip transport. A well-balanced dimensioning of the bonding area will result in a successful machine concept (Figure 3).

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As an alternative, various manufacturers employ indirect RFID chip assembly. Indirect assembly, as a first process step, introduces a flip-chip interposer. In a subsequent step, at very high throughput and low cost of ownership, the interposer is mounted on the antenna, which can be done by crimping. Indirect assembly is advantageous especially for manufacturers that have no previous experience with bare-chip processing and do not want to invest in gathering the necessary know-how. At the same time, investment costs for the followup assembly step are significantly lower. The tradeoff here is higher packaging costs. Also, crimp connection quality is still a very controversial matter. Therefore, alternative methods such as soldering or adhesive interconnection methods are being used. Alternatively, the connection is facilitated after the interposer is glued onto cardboard and the antenna is applied in a second step via the printing of conductive ink over both cardboard and interposer.

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Interconnection Methods

Users also must choose the type of interconnection method. Figure 4 (online) shows various options available. In terms of RFID chip assembly, the most promising technologies are NCA (non-conductive adhesive) and ACA (anisotropic conductive adhesive). (3) Because the pre-applied epoxy also functions as an underfill, the interconnection technology is very cost-effective, especially in paste form (NCP, ACP). The epoxy can be applied by screen printing or dispensing, whereby dispensing saves further costs because the process consumes less material. Bearing in mind that NCP is less expensive than ACP, the ideal interconnection technology seems to be dispensed NCP. Advantages of NCP are:

* Easy, fast, low-cost processing.

* High-quality interconnection.

* No additional underfill.

* Few process steps.

* Low epoxy cost.

* Heat compliant with low-cost substrate materials.

* Usable for reel-to-reel applications.

The feasibility of high-volume NCP production on flex substrate has been demonstrated in smartcard production, where the reliability requirements of flip-chip packages has been proven.

In addition, the non-collapse soldering process is used for RFID chip assembly. For example, gold bump soldering (GBS) benefits from the low bumping costs of the gold bump and the high quality of the intermetallic interconnection due to soldering.

To complete the picture: Collapse processes are not feasible because of higher bumping costs, thicker package profiles and the need for an extra underfill step, unless pre-applied underfill is used. The ICA process is inferior because it requires the extra underfill step. Ultrasonic and thermosonic require mechanically stable support from the substrate, which is not easy to achieve with low-cost materials like PET at thicknesses of 50 [micro]m and below.

Hugo Pristauz is manager, advanced technology and business development, RFID, Datacon Technology GmbH (datacon.at); [e-mail].